面向高性能计算的多通道交织存储架构设计

为解决雷达、电子对抗等高性能计算应用中的存储访问带宽瓶颈,文中设计了一种多通道交织的存储架构,通过存储通道间的地址交织映射和集中式调度器的拆分与重组,实现了多个物理存储通道的并发访问,成倍提高了访存带宽,并具有良好的可配置和可扩展特性。该设计充分利用市场现有成熟的单通道控制器技术,经济高效。为评估性能,以4通道存储系统为例,建立了周期精确的RTL模型及其仿真验证环境。测试结果显示,交织粒度在64 B~512 B内系统获得最优性能,该性能是目前广泛采用的独立多通道存储架构性能的约4倍。     

Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach

We present a high qualitative reconfigurability method for fault-tolerant memory systems against radiation influence on semiconductors. Its novelty lies in a joint failure repair mechanism. It uses a concurrent on-line technique based on asynchronous built-in current sensors (BICS), parity check and cold spare modules against electrical abnormal behaviour due to latch-up (LU), and the Hamming SEC code to counterattack single error upset (SEU), manifested in logical failures. Complete reliability computations, which underlie the proposed scheme, search for a 99.902% tolerance, thought to meet typical spatial irradiation conditions, to the cost of a small hardware overhead (2 spare (additional) 1K1 modules for each 1K16 of a memory system of 512K16, and Mean Time To Failure = 10–7 h–1). Finally, as we envisage a 2.4 m CMOS implementation, we performed complexity estimations, which show that the supplementary self-tolerance ensuring circuitry involves an overhead of 0.0094% for a 512K16 memory. The recovering latency is minimised. For SEU in DRAM it requires zero latency and no more than the duration of an equivalent refresh cycle in SRAM. LU reflects a locality property, as only the affected module is submitted to the recovering algorithm.     

Memory Reliability Improvement Based on Maximized Error-Correcting Codes

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable.     

A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage V_PGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at V_CC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at V_CC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application.     

A low power CMOS compatible embedded EEPROM for passive RFID tag

A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18 μm CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018 mm² and consumes 14.5 and 370 μW for read and write at 85 °C, respectively.     

Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems

Continuous scaling of conventional hard-wired metal interconnects into deep sub-micrometer region (DSM) has resulted in significant performance degradation in terms of delay, crosstalk noise, higher power dissipation, and decreased tolerance to noise. Besides, communication-centric nature of system-on-chip (SOC) networks requires efficient intra- and inter-chip interconnect technologies. Radio-frequency (RF)/wireless interconnects promise to be the best alternative to metal interconnects as they are compatible with current CMOS-technology, and they also provide higher data rate and bi-directional multi I/O transmissions. This paper evaluates the system bit-error-rate (BER) performance with the application of fault-tolerance capability using linear error-control codes (ECCs) within chip (intra-chip) RF/wireless interconnect systems. It also evaluates the utility of ECCs by considering energy consumed in ECC encoding-decoding vis-à-vis the energy saved due to coding gain by calculating the critical distance (d_cr). The results indicate that for a certain range of received signal-to-noise ratio (SNR), application of ECC improves the BER performance of the RF/wireless interconnect system. It is also shown that d_cr drops to 0.7 mm at 18 GHz.     

CMMB标准中RS编码的FPGA实现

简要介绍了移动电视传输标准CMMB中RS(里德-索罗门)编码的特点.采用Matlab进行算法验证,并用FPGA实现.字节交织使用乒乓流水线结构,缩短了等待时间.针对k=176设计出节约成本的编码器.提出利用VGA接口获取FPGA验证数据源,使用"编码-解码-重现"的模式对RS编码器充分验证.     

基于STM32处理器的存储器IAP编程技术

本文针对存储器程序更新的问题,提出一种基于STM32的IAP程序更新方法-通过STM32的FSMC接口实现NOR Flash访问,并以JFM-F512K32芯片为例,说明FSMC接口的配置方法,通过IAP程序运行实现Flash存储器数据的更新.该设计成功实现Flash程序的自动更新功能,操作简单、速度快、正确率高.     

A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit

A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

N-modular redundancy using the theory of error correcting codes

Using redundancy is basic to fault-tolerant computing. N-modular redundancy (NMR) is in some ways analogous to the use of a repetition code where an information symbol is replicated as parity symbols in a codeword. Linear error-correcting codes (ECC) use linear combinations of information symbols as parity symbols to generate syndromes for error patterns. In this paper, ECC theory has been applied to derive redundant circuits that tolerate faults in both the modules and checkers. Circuits using comparators for diagnosis are derived with a non-graph-theoretic approach. Coding theoretic principles are applied directly to NMR, so that extensive diagnosis of the fault-tolerant system is achieved.     

A Chaotic Interleaving Scheme for the Continuous Phase Modulation Based Single-Carrier Frequency-Domain Equalization System

In this paper, we propose a chaotic interleaving scheme for the continuous phase modulation based single-carrier frequency-domain equalization (CPM-SC-FDE) system. Chaotic interleaving is used in this scheme to generate permuted versions from the sample sequences to be transmitted, with low correlation among their samples, and hence a better bit error rate (BER) performance can be obtained. The proposed CPM-SC-FDE system with chaotic interleaving combines the advantages of the frequency diversity, the low complexity, and the high power efficiency of the CPM-SC-FDE system and the performance improvements due to chaotic interleaving. The BER performance of the CPM-SC-FDE system with and without chaotic interleaving is evaluated by computer simulations. Also, a comparison between the proposed chaotic interleaving and the conventional block interleaving is performed. Simulation results show that, the proposed chaotic interleaving scheme can greatly improve the performance of the CPM-SC-FDE system. Furthermore, the results show that this scheme outperforms the conventional block interleaving scheme in the CPM-SC-FDE system. The results also show that, the proposed CPM-SC-FDE system with chaotic interleaving provides a good trade-off between system performance and bandwidth efficiency.     

Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect

In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8 V, digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8 Gb/s data transfer rate over a FR4 PCB trace of length 7.5 in. for a target bit-error rate (BER) of 10⁻¹². The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100 MHz to 20 GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are and 5.34 mV, respectively. The standalone power consumption of the hybrid is 14.64 mW.     

SSD‐enhanced uncoded space‐time labeling diversity

Space‐time labeling diversity (STLD) has been shown to be an efficient technique for improving the bit error rate (BER) performance of an uncoded space‐time coded modulation system. In this paper, signal space diversity (SSD) is incorporated into the uncoded STLD system to further enhance the system BER performance. A tight closed‐form union bound on the BER of the proposed system is derived and is used to optimize the rotation angle of the SSD scheme. Simulation results are used to confirm the theoretical bound derived for the system. The results also show performance gains of approximately 2.0 dB at a BER of 10^?6 and 1.6 dB at a BER 10^?4 from incorporating SSD into the uncoded STLD system using 16QAM and 64QAM, respectively. Furthermore, a low complexity detection scheme based on orthogonal projection is formulated for the proposed scheme and, in comparison with the optimal maximum‐likelihood detector, is shown to result in a 56% and 95% reduction in computation complexity for the 16QAM and 64QAM versions of the proposed system, respectively.     

Performance analysis of adaptive interleaving for OFDM systems

We proposed a novel interleaving technique for orthogonal frequency division multiplexing (OFDM), namely adaptive interleaving, which can break the bursty channel errors more effectively than traditional block interleaving. The technique rearranges the symbols according to instantaneous channel state information of the OFDM subcarriers so as to reduce or minimize the bit error rate (BER) of each OFDM frame. It is well suited to OFDM systems because the channel state information (CSI) values of the whole frame could be estimated at once when transmitted symbols are framed in the frequency dimension. Extensive simulations show that the proposed scheme can greatly improve the performance of the coded modulation systems utilizing block interleaving. Furthermore, we show that the adaptive interleaving out performs any other static interleaving schemes, even in the fast fading channel (with independent fading between symbols). We derived a semi-analytical bound for the BER of the adaptive interleaving scheme under correlated Rayleigh fading channels. Furthermore, we discussed the transmitter-receiver (interleaving pattern) synchronization problem     

A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram

Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, very low standby power and high storage density. Multi-level Cell (MLC) PRAM, which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As a first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error control coding (ECC) scheme can be used for half of the bits. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the remaining bits. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the proposed multi-tiered approach enables us to use ECC with 2-error correction capability (t?=?2) instead of one with t?=?8 to achieve a block failure rate (BFR) of 10^?8. We propose to use a non-iterative algorithm to implement the BCH t?=?2 decoder because of its small latency. We evaluate the latency and energy overhead of the proposed scheme using CACTI and the IPC performance using GEM5. We show that for SPEC CINT 2006 and DaCapo benchmarks, the proposed system can achieve BFR = 10^?8 with 2.2 % IPC reduction and 7 % additional energy compared to a memory without any error correction capability.     

有限反馈预编码优化中基于性能准则的码字选择

多输入多输出(MIMO)空分复用系统中,采用有限比特反馈方式设计最优预编码矩阵,使用较少的反馈开销,可以有效地提高系统性能。对于有限反馈预编码设计方案,提出了一种基于Qos准则的码字选择方法,以最优化系统MSE性能和BER性能为目标选择最佳码字。仿真结果表明,与已有的码字选择方式相比,本文提出的方法更加直接,对于各种码本具有通用性,而且进一步改善了有限比特反馈预编码的性能,系统BER值降低了1.5 dB。     

Multistage recursive interleaver for turbo codes in DS-CDMA mobileradio

A multistage recursive block interleaver (MIL) is proposed for the turbo code internal interleaver. Unlike conventional block interleavers, the MIL repeats permutations of rows and columns in a recursive manner until reaching the final interleaving length. The bit error rate (BER) and frame error rate (FER) performance with turbo coding and MIL under frequency-selective Rayleigh fading are evaluated by computer simulation for direct-sequence code-division multiple-access mobile radio. The performance of rate-1/3 turbo codes with MIL is compared with pseudorandom and S-random interleavers assuming a spreading chip rate of 4.096 Mcps and an information bit rate of 32 kbps. When the interleaving length is 3068 bits, turbo coding with MIL outperforms the pseudorandom interleaver by 0.4 dB at an average BER of 10^-6 on a fading channel using the ITU-R defined Vehicular-B power-delay profile with the maximum Doppler frequency of f_D = 80 Hz. The results also show that turbo coding with MIL provides superior performance to convolutional and Reed-Solomon concatenated coding; the gain over concatenated coding is as much as 0.6 dB     

Hybrid ARQ scheme using interleaved Reed-Solomon codes in apower-controlled DS-CDMA cellular system

A new hybrid automatic repeat request (ARQ) scheme is proposed for data transmission in a power-controlled direct sequence (DS) code division multiple access (CDMA) system cellular system. The data frame is composed of interleaved Reed-Solomon codes. The depth of interleaving is determined by a power-control interval. After decoding each codeword with algebraic decoding, the post-decoding processor decides whether to accept the codeword or to discard it by using channel state information from the power-control processor. The proposed hybrid ARQ scheme significantly reduces the probability of undetected error among accepted codewords without significantly reducing the throughput     

Fast and scalable parallel layout decomposition in double patterning lithography

For 32/22 nm technology nodes and below, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising and show the presented parallel layout decomposition methods obtain upto 21× speedup in runtime and upto 7.5×reduction in peak memory consumption with acceptable solution quality.