Influence of the manufacturing process on the electrical properties of thin (<4 nm) Hafnium based high-k stacks observed with CAFM

In this work, the dependence of the electrical characteristics of some thin (<4 nm) HfO₂, HfSiO and HfO₂/SiO₂ stacks on their manufacturing process is studied at the nanoscale. Topography, current maps and current–voltage (I–V) characteristics have been collected by conductive atomic force microscope (CAFM), which show that their conductivity depends on some manufacturing parameters. Increasing the annealing temperature, physical thickness or Hafnium content makes the structure less conductive.     

An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode

Ni-germanosilicided Schottky barrier diode has been fabricated by annealing the deposited Ni film on strained-Si and characterized electrically in the temperature range of 125 K–300 K. The chemical phases and morphology of the germanosilicided films were studied by using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). The Schottky barrier height (_b), ideality factor (n) and interface state density (D_it) have been determined from the current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The current–voltage characteristics have also been simulated using SEMICAD device simulator to model the Schottky junction. An interfacial layer and a series resistance were included in the diode model to achieve a better agreement with the experimental data. It has been found that the barrier height values extracted from the I–V and C–V characteristics are different, indicating the existence of an in-homogeneous Schottky interface. Results are also compared with bulk-Si Schottky diode processed in the same run. The variation of electrical properties between the strained- and bulk-Si Schottky diodes has been attributed to the presence of out-diffused Ge at the interface.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

Electrical properties in low temperature range (5 K–300 K) of Tantalum Oxide dielectric MIM capacitors

Tantalum oxide (Ta₂O₅) is widely used for MIM (Metal-Insulator-Metal) capacitor owing of its high dielectric constant. This work examines current–voltage and capacitance–voltage characteristics in the 5 K–300 K temperature range. Working at low temperature was chosen in order to freeze trapping mechanisms of the MIM capacitor. The curvature of C–V characteristics radically changes from 5 K to 300 K. The capacitance variation under voltage at 50 K and below can be investigated using the Langevin theory. From this model the permanent dipole moment and the number of dipoles have been extracted. From Poole–Frenkel identification curves, activation energy around 0.20 eV and a dielectric constant of 26 were found for positive polarisation. However, conduction mechanisms cannot be reduced to strick Poole–Frenkel modelling.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Circuit implications of gate oxide breakdown

A model for the oxide breakdown (BD) current–voltage (I–V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains.     

Ballistic electron emission microscopy studies of the temperature dependence of Schottky barrier height distribution in CoSi2/n-Si(1 0 0) diodes formed by solid phase reaction

Ballistic electron emission microscopy (BEEM) and ballistic electron emission spectroscopy have been performed on polycrystalline and epitaxial CoSi₂/n-Si(1 0 0) contacts at temperatures ranging from −144°C to −20°C. The ultra-thin CoSi₂ films (10 nm) were fabricated by solid state reaction of a single layer of Co (3 nm) or a multilayer of Ti (1 nm)/Co (3 nm)/amorphous-Si(1 nm)/Ti (1 nm) with a Si substrate, respectively. The spatial distribution of barrier height over the contact area obeys a Gaussian function at each temperature. The mean barrier height increases almost linearly with decreasing temperature with a coefficient of −0.23±0.02 meV/K for polycrystalline CoSi₂/Si diodes and −0.13±0.03 meV/K for epitaxial diodes. This is approximately equal to one or one-half of the temperature coefficient of the indirect energy gap in Si, respectively. It suggests that the Fermi level is pinned to different band positions of Si. The width of the Gaussian distribution is about 30–40 meV, without clear dependence on the temperature. The results obtained from conventional current–voltage and capacitance–voltage (I–V/C–V) measurements are compared to BEEM results.     

Breakdown spots of ultra-thin (EOT < 1.5 nm) HfO2/SiO2 stacks observed with enhanced—CAFM

In this work, the (gate) current versus (gate) voltage (I–V) characteristics and the dielectric breakdown (BD) of an ultra-thin HfO₂/SiO₂ stack is studied by enhanced conductive atomic force microscopy (ECAFM). The ECAFM is a CAFM with extended electrical performance. Using this new set up, different conduction modes have been observed before BD. The study of the BD spots has revealed that, as for SiO₂, the BD of the stack leads to modifications in the topography images and high conductive spots in the current images. The height of the hillocks observed in the topography images has been considered an indicator of structural damage.     

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO₂ gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, ΔV_TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO₂ interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO₂ interface (P_b centers) and its vicinity (E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I_D − V_G (ΔV_TH) techniques, however, suggests that ΔV_TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO₂/SiO₂ gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO₂ and high-k gate stacks suggesting a common mechanism of the interface degradation.     

n-Al0.15Ga0.85 N/p-6H–SiC heterostructure and based bipolar transistor

Heterojunction bipolar transistor (HBTs) based on Al0.15Ga0.85 N/6H–SiC heterojunction was fabricated. Room-temperature current–voltage (I–V) characteristics of n-Al0.15Ga0.85 N/p-6H–SiC emitter–base heterojunction exhibited good rectifying behavior with a forward current 5 × 10⁻² A and reverse current 3 × 10⁻⁹ A at 10 V and −10 V, respectively. Analysis of the temperature dependent I–V characteristics of this heterojunction revealed a barrier height of 1.1 eV. The fabricated n-Al0.15Ga0.85 N/p-SiC/n-SiC bipolar transistor did not exhibit common-emitter operation, however, common-base operation was observed with current gain β = IC/IB ranging in 75–100.     

Characterization by Internal Photoemission Spectroscopy of Single-Crystal CVD Diamond Schottky Barrier Diodes

Internal photoemission spectroscopy measurements have been performed to study the electrical characteristics of Schottky diodes on boron-doped single-crystalline chemical vapor deposited (SC-CVD) diamond. These measurements were compared with current–voltage (I–V) and current–temperature (I–T) measurements. Schottky contact barrier heights and ideality factors have been measured on Schottky contacts formed on four samples with Au, Ni, and Al contact metallizations. I–V and I–T measurements were performed in the temperature range from 300 K to 500 K. The internal photoemission method, which is less influenced by local variations in the Schottky barrier height than the other two methods, yielded the highest values of Schottky barrier heights to p-type material: Φ_B = 1.78 eV to 2.10 eV, depending on the choice of contact metal and sample boron concentration.     

Temperature-dependence of barrier height of swift heavy ion irradiated Au/n-Si Schottky structure

The electrical characteristics of swift heavy ion (SHI) irradiated Au/n-Si (1 0 0) structure has been investigated in a wide temperature range (50–300 K). The forward bias current–voltage (I–V) measurements have been used to extract the diode parameters as a function of temperature. The Zero-bias Schottky barrier height decreases with decreasing temperature. However, the flat-band barrier height is almost independent of the temperature. These results are interpreted using the models of Fermi level pinning. The behavior of Schottky diode parameters is explained by taking into account the role of the irradiation induced defects at Au/n-Si (1 0 0) interface.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.     

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V_D=1.8 V. We present a comprehensive study on the I–V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET (V_thn) of between 0.70 and 0.72 V and a saturation current (I_DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V_thn of between 0.85 and 0.90 V and an I_DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V_g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.     

Optical and electrical characterization of hafnium oxide deposited by liquid injection atomic layer deposition

Optical and electrical properties of a set of high-k dielectric HfO₂ films, deposited by liquid injection atomic layer deposition (LI-ALD) and post deposition annealed (PDA) in nitrogen (N₂) ambient at various temperatures (400–600 °C), were investigated. The films were prepared using the cyclopentadienyl of hafnium precursor [Cp₂Hf(CH₃)₂] with water deposited at 340 °C. The spectroscopic ellipsometric (SE) results show that the characteristics of the dielectric functions of these films are strongly affected by annealing temperatures. I–V results show that N₂-based PDA enhances the average energy depth of the shallow trapping defects from Poole–Frenkel conduction fitting. This also correlated with the measured increase in MOS capacitance–voltage hysteresis.     

Single band electronic conduction in hafnium oxide prepared by atomic layer deposition

Current–voltage and capacitance–voltage measurements on MOS structures with hafnium gate oxide (HfO₂) prepared by atomic layer deposition were conducted to determine the dominant current conduction in the Al/HfO₂/Si structure. In n-type substrate MOS structures, electron injection from Al into HfO₂ is observed when the Al electrode is negatively biased. Whereas in p-type MOS capacitors at negative biasing, no hole injection can be detected and the current in the insulator is again due to the electron injection from Al. These results unambiguously indicate that in both p- and n-type substrates and at both biasing polarities only electronic current conduction in the Si/HfO₂/Al is significant.     

Progressive breakdown in ultrathin SiON dielectrics and its effect on transistor performance

The post-breakdown conduction properties of ultrathin SiON layers were investigated, to determine the impact of various parameters on the growth of a breakdown path after its formation. Post-breakdown conduction is seen to be dependent on stress voltage used to break the oxide, the stress temperature, and the time-to-breakdown. With this knowledge, the performance of transistors of various channel lengths and widths was studied both before and after breakdown occurred to determine whether the devices still function as a digital switches after breakdown. That is, the drain to source current (I_ds) in the on–state (V_g V_th) is much larger than I_ds in the off–state (V_g < V_th), allowing the device to continue to function as a switch, after breakdown occurs.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

Electrical characterization of hafnium oxide and hafnium-rich silicate films grown by atomic layer deposition

An electrical characterization comparative analysis between Al/HfO₂/n-Si and Al/Hf-Si-O/n-Si samples has been carried out. Hafnium-based dielectric films have been grown by means of atomic layer deposition (ALD). Interface quality have been determined by using capacitance–voltage (C–V), deep level transient spectroscopy (DLTS) and conductance transient (G-t) techniques. Our results show that silicate films exhibit less flat-band voltage shift and hysteresis effect, and so lower disordered induced gap states (DIGS) density than oxide films, but interfacial state density is greater in Hf–Si–O than in HfO₂. Moreover, a post-deposition annealing in vacuum under N₂ flow for 1 min, at temperatures between 600 and 730 °C diminishes interfacial state density of Hf–Si–O films to values measured in HfO₂ films, without degrade the interface quality in terms of DIGS.