An analytic model for thin SOI transistors

A simple charge sheet model is shown to provide a surprisingly accurate approximation to the behavior of a long-channel FET fabricated in a silicon-on-insulator (SOI) structure with a very thin silicon film. Using this charge sheet model, an accurate calculation of the I-V characteristics of transistors fabricated in these thin films is derived. Included in the results is an expression for the threshold voltage which shows, among other things, that the threshold voltage of suitably designed transistors is only logarithmically dependent on the thickness of the silicon film     

Analysis of temperature dependence of CMOS transistors' threshold voltage

In this paper an investigation of influence of the metal-semiconductor work function difference on the threshold voltage of high-temperature (up to 473 K) operating CMOS transistors, which is often neglected in the literature, is presented. Expressions for temperature dependence of the threshold voltage of both Al-gate and Si-gate CMOS transistors, which take into account the influence of the metal-semiconductor work function difference, are derived starting from the standard expression for the MOS transistor threshold voltage. The temperature coefficient of the threshold voltage is considered in more detail, to provide a simple approximate model for the temperature dependence of the threshold voltage. It is shown that neglecting the temperature dependence of the metal-semiconductor work function difference significantly affects accuracy in prediction of the threshold voltage temperature behavior.     

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.     

双栅无结晶体管阈值电压模型

无结晶体管是近年来纳米SOI MOS器件领域的研究热点,相对于传统晶体管具有明显的优势。本文针对全耗尽型无结晶体管,基于二维泊松方程,建立了电势分布解析模型。根据该模型可以得到阈值电压模型。利用建立的解析模型和半导体器件仿真软件MEDICI,探讨了栅压和器件结构参数对电势分布和阈值电压的影响。该模型简单且与仿真结果吻合良好。     

An efficient method for determining threshold voltage, seriesresistance and effective geometry of MOS transistors

An accurate and robust method of extracting the threshold voltage, the series resistance and the effective geometry of MOS transistors is presented. The method is based on efficient nonlinear optimization using an iterative linear regression procedure which usually converges in less than four rounds. Thereby extracted parameters are obtained from analytical expressions for the solutions to a linear system of equations whereby time consuming numerical differentiations are avoided. MOSFET parameters are explicitly identified as parameters of an underlying widely used device model that is a good approximation for operation in the linear region. The method is particularly suitable for process characterization and can be used on as few as twelve data points (three data points from each of four different size transistors). By connecting external resistors in series with the transistors, we show that the extracted values of the parameters are independent of the series resistance     

Substrate bias dependence of short-channel MOSFET thresholdvoltage-a novel approach

A simple theory to predict the threshold voltage variation of short-channel MOS transistors with substrate bias is proposed. While the basis of the model is vertical field perturbations due to the source-drain, its uniqueness depends on a definition of threshold voltage based on the amount of total free charge in the channel rather than inversion of the entire channel. The theory has been verified for transistors of three channel lengths, namely 2.70, 1.70, and 0.70 μm, fabricated with a p-well CMOS process. A comparison is made with an earlier model based on field perturbation. The validity of the arguments underlying the theory has been demonstrated by 2-D device simulations with MINIMOS     

Two-dimensional finite element charge-sheet model of a short-channel MOS transistor

A two-dimensional charge-sheet model for short-channel MOS transistors has been developed. The unique feature of the model is that the effect of channel inversion layer charge is included as a nonlinear integral boundary condition on the two-dimensional electrostatic field in the transistor. The average inversion layer charge density and source-drain current are obtained directly from the model rather than from the electron density or electron quasi-Fermi level. The model retains all of the physical detail of more complex two-dimensional models such as sensitivity to source-drain profile shape, channel profile, and oxide field shape. This allows the model to represent the changes in drain current associated with short-channel effects while still allowing simple comparison with long-channel models. For long-channel transistors, the results of this model are identical to Brews' long-channel charge-sheet model. The accuracy of this model is verified by modeling a sequence of transistors with channel lengths between 4.6 and 1.1 μm. In short-channel transistors, effects previously attributed to high field mobility are explained by simple two-dimensional electrostatics.The simulations produced using this model have been compared to experimental measurements on an array of n-channel MOSFETs; the model is in good agreement for transistors with channel lengths as short as 1.1 μm. In this verification process, the model represented accurately the onset of subthreshold current, channel-length-induced threshold voltage offset, and drain-field-induced output conductance changes.From studies of numerical accuracy, we conclude that the charge-sheet model can easily simulate drain current with an accuracy which exceeds that required for most applications. To obtain 5% accuracy for drain current, a 146 element mesh is sufficient. Refinement of the 146 element mesh to a 455 element mesh gives a current which is accurate to 0.16%. Average computer time for a high current solution is 2.5 min on a DEC-20.The numerical solutions were obtained using general-purpose software for solving elliptic partial differential equations. We have been able to solve problems with exact solutions to test the correctness and accuracy of our codes. We also can easily change the physics included in our model and the geometry of the transistor. The finite element method used allows refinement of oblique triangles which is important in achieving computational efficiency. The program is portable and has been run on a DEC-20, a VAX $\text{11}\text{780}$, a Cyber 175 and a Univac 1108.     

Delay caused by resistive opens in interconnecting lines

An accurate electrical fault characterization is required for the correct diagnosis and localization of CMOS interconnect defects. It has been traditionally accepted that a resistive open defect located at the beginning of an interconnecting line causes the maximum possible delay. The first-order approximation is sufficient to model the behaviour of high resistive opens. However, in this paper it is shown that low resistive opens do not follow this behaviour. In these cases, a second-order model is required for a more precise prediction of their defective behaviour, since the maximum delay is obtained for an intermediate location, which depends on the relationship between the open resistance, the on-resistance of the transistor network driving the defective net, the parasitic capacitances and the threshold voltage of the transistors driven by the defective net. For that purpose, an experimental circuit has been designed and fabricated where open defects have been intentionally added in a set of interconnect CMOS lines. Both simulation and experimental results on defective interconnect lines show maximum delays for opens located at intermediate positions provided that the resistance of the open is on the order of the on-resistance of the driving transistor network.     

Simulation and fabrication of submicron channel length DMOStransistors for analog applications

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1-μm-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7° implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator     

A comprehensive submicrometer MOST delay model and its applicationto CMOS buffers

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-μm CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits     

环栅结构CMOS/SOI器件SPICE模型研究

建立了环栅结构的CMOS/SOI器件的SPICE模型,可以对抗辐照设计中环栅结构的CMOS/SOI器件计算其等效宽长比,将环栅器件转换为等效宽度和长度的条栅器件;以及对体接触电阻等其他受影响的SPICE模型参数做出调整,使其电学特性模拟达到最准确精度.模拟数据和试验数据具有很好的一致性,证明所建立的模型具有较高的精度.     

全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型.基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解.同时利用阈值电压的定义得到了阈值电压的模型.该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应.为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟.结果表明,模型计算与软件模拟吻合较好.     

全耗尽SOI MOSFETs阈值电压和电势分布的温度模型

提出了一个全耗尽SOI MOSFETs器件阈值电压和电势分布的温度模型. 基于近似的抛物线电势分布模型,利用适当的边界条件对二维的泊松方程进行求解. 同时利用阈值电压的定义得到了阈值电压的模型. 该温度模型详细地研究了电势分布和阈值电压跟温度之间的变化关系,同时还近似地探讨了短沟道效应. 为了进一步验证模型的正确性,利用SILVACO ATAS软件进行了相应的模拟. 结果表明,模型计算与软件模拟吻合较好.     

A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary analysis, taking into account both the "front coupling" (variation of the front-channel threshold voltage V_T1, as a function of the substrate bias V_G2) and "back coupling" (variation of the back-channel threshold voltage V_T2) as a function of the front-gate bias V_G1) characteristics has been carried out. It is shown that the back coupling, as opposed to the front coupling, is highly sensitive to the fin width in narrow-channel devices and can even be used in fin width extraction. Simple analytical 2-D models for the body potential, V_T1, and V_T2 have been developed to clarify the experimental data, showing in particular the gradual control of the back interface potential by the lateral gates in narrow fins. The model stands as a 2-D generalization of the Lim and Fossum's well-known 1-D interface coupling model     

Characteristics of amorphous-silicon distributed-threshold voltagetransistors formed by ion implantation

Hot ion-implantation has been applied to threshold voltage control of amorphous-silicon thin-film transistors. A threshold voltage shift as large as 13 V has been achieved without deterioration of the field-effect mobility. The technique was also used to form distributed-threshold voltage transistors which have a microstructure inside the channel. It was verified that the off-characteristics were greatly improved     

全耗尽SOIMOSFET辐照导致的阈值电压漂移模型

报道了全耗尽SOI MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的加固SOI器件与电路的模拟.讨论了抑制阈值电压漂移的方法.结果表明,对于全耗尽SOI加固工艺,辐照导致的埋氧层(BOX)氧化物电荷对前栅的耦合是影响前栅阈值电压漂移的主要因素,但减薄埋氧层厚度并不能明显提高SOI MOSFET的抗辐照性能.     

A closed-form delay expression for digital BiCMOS circuits withhigh-injection effects

A non-iterative formula is derived for calculating the delay time of digital BICMOS circuits with their bipolar transistors operating in high-current regime. Effects such as the base transit-time increase of minority carriers and the decrease of the current gain of the bipolar transistors are all incorporated in the model. This model can be used to investigate the effects of most device parameters such as transistor sizes and external loading on the performance of the circuits without resorting to any iterative procedures. This simplified model compares well with the original model to 10% over a wide range of operating conditions, and is especially accurate for situations where base widening affects the bipolar transistors     

A new charge-control model for single- and double-heterojunctionbipolar transistors

A new charge-control relation is derived for heterojunction bipolar transistors. The relation is valid for arbitrary doping density profiles and for all levels of injection in the base. It is applicable to both single- and double-heterojunction transistors. The model is an improvement over another recently proposed charge-control model that was valid only for constant doping density and low injection in the base. Large- and small-signal equivalent circuit models are also presented for heterojunction bipolar transistors. Comparisons with numerical and experimental data show excellent agreement     

A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction

After differences between the RF MOSFET and conventional high-frequency transistors, which make the proper modeling of RF MOSFET complicated and difficult, are addressed, a four-terminal small-signal model of an RF MOSFET with a very simple and accurate parameter extraction method is presented. This model includes the intrinsic and extrinsic elements important for RF AC simulation in the strong inversion operation region. Accuracy of the model and extraction method is verified with the measured data and the needs of the intrinsic body node are demonstrated to describe the gate bias dependence of the substrate-signal-coupling effect.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.