零中频DVB-H调谐器中信道选择滤波器的设计

介绍了零中频结构DVB-H调谐器中信道选择滤波器及其自动频率校准电路的设计.该滤波器采用7阶切比雪夫(Chebyshev)I型低通结构,截止频率3/3.5/4 MHz可编程;在偏离截止频率1.25/4 MHz的频点上,分别实现24/56 dB衰减.为了补偿RC常数漂移,设计了一个基于逐渐近似 (SAR) 算法的自动频率校准电路,在N比特精度下,仅需要N个时钟周期就能完成校准.相比传统技术,明显提高了校准速度.基于TSMC 90 nm 数字CMOS工艺,在1.2 V电源电压下进行了仿真实验.结果表明,滤波器的输入等效噪声为48 nV/Hz,三阶交调点(IIP3)达到26 dBm,频率校准精度在2.5%以内,功耗为16 mW.     

用于LTE的宽带有源RC低通滤波器设计

本文介绍了一种高线性带宽可配置(10/50MHz)的低通滤波器。该滤波器为六阶切比雪夫-Ⅰ有源RC结构。采用了一种新型的运算放大器补偿技术,使得滤波器在合理的功耗和较高截止频率(50MHz)下仍有很好的邻带抑制特性。采用0.18um CMOS工艺流片验证,测试结果表明：在10MHz截止频率下,12.5MHz处邻带抑制15.3dB;在50MHz截止频率下,60MHz处邻带抑制8.3dB,3倍频带外抑制大于60dB,带内纹波小于1dB。     

UHF RFID阅读器中可编程全差分低通滤波器的设计

基于TSMC 0.25 μm RF CMOS工艺,提出了一种应用于860～960 MHz UHF波段单片射频识别(RFID)阅读器的可编程全差分低通滤波器电路.该滤波器为6阶切比雪夫有源RC滤波器,其中的运放采用带共模反馈的全平衡差动放大器结构(FBDDA)实现了全差分的缓冲器.仿真结果表明:该电路可以通过3位信号控制位产生截止频率为400 kHz、600 kHz、800 kHz、1 MHz以及1.3 MHz的全差分低通滤波器,1 MHz处的点噪声为20 nV/Hz,1 dB输入压缩点为15 dBm,3.3 V电源电压下电路消耗总电流为4.86 mA.     

射频识别阅读器中信道选择滤波器的设计

基于IBM0.18μm标准CMOS工艺,设计了一种适用于UHF RFID(Radio Frequency Identification)阅读器的信道选择滤波器。这种滤波器和其他结构滤波器相比,可以获得更高的线性度和更好的噪声特性。设计中,低通滤波器截止频率0.3~1.3 MHz范围内可调。当截止频率设置为900 kHz时,带内增益稳定在0 dB,在1.8 MHz频率处具有大于49 dB的幅度衰减。     

一种0.18 μm CMOS模拟滤波器的设计与实现

基于0.18 μm CMOS工艺,实现了一种6阶有源RC模拟滤波器,截止频率可以配置为1.25 MHz/2.5 MHz/5 MHz/10 MHz,增益可以配置为0 dB/6 dB/12 dB/18 dB,能够应用于WiMAX/WLAN接收机。采用一种新型的自动频率校准电路,使滤波器的截止频率不受工艺变化的影响。测试结果表明,在1.8 V电源电压下,消耗电流16 mA,输入3阶交调为23.4 dBm。正交两路模拟滤波器与频率校准电路所占面积为0.38 mm²。     

基于CMMB标准的自校正CMOS椭圆低通Gm-C滤波器

提出了一种基于CMMB(中国移动多媒体广播)标准的9阶椭圆函数Gm-C滤波器结构.该滤波器截止频率为3.75MHz,通带波纹小于1dB,过渡带宽500kHz,在4.25MHz处衰减达40dB以上,功耗为7mW.采用0.25μmCMOS工艺,在自动校正电路的作用下,该滤波器在工艺偏差(温度在-40～90℃交化以及±10%的电源电压偏差)的情况下也能保持良好的性能,截止频率偏差不超过1%,临近信道抑制超过40dB.     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.     

应用于直接变频架构直播卫星调谐器中的具有宽调谐范围的连续时间低通滤波器

本文用0.35微米锗硅BiCMOS工艺设计了七阶巴特沃兹跨导电容低通滤波器及其片上自动调谐电路,该低通滤波器适用于采用直接变频架构的直播卫星调谐器。该滤波器的-3dB带宽截止频率具有从4MHz到40MHz的宽调谐范围。成功实现了一种新颖的片上自动调谐方案,用来调谐和锁定滤波器的-3dB带宽截止频率。测试结果表明,该滤波器具有-0.5dB的通带电压增益,+/- 5%的带宽精度,30nV/Hz1/2的等效输入噪声,-3dBVrms 通带电压三阶交调点,27dBVrms 阻带电压三阶交调点。I/Q正交两路滤波器及其调谐电路采用5V电源,在滤波器的-3dB带宽截止频率为20MHz的情况下,消耗电流13毫安,占用芯片面积0.5mm2。     

具有片上数字控制频率调谐的9MHz有源RC滤波器

讨论了适用于无线局域网零中频收信机的4阶切比雪夫有源RC滤波器,为消除工艺偏差和环境变化对截止频率的影响,提出片上数字控制频率调谐电路.采用TSMC-0.25μm 1P5M CMOS工艺进行制造,测得调谐锁定时,滤波器的截止频率为9MHz,通带增益为0dB,增益波动小于1dB,带外抑制在30MHz处小于-40dB,通带内噪声小于-142dBm/Hz,当两输入信号的功率为-10dBm时,三阶交调小于-70dBm.     

DDS信号发生器中椭圆低通滤波器的设计

给出了利用DDS技术对DDS信号发生器中低通滤波器进行设计的一般方法,该方法采用截止特性陡峭的7阶椭圆函数低通滤波器,该滤波器的3 dB截止频率为120 MHz,在145MHz处的衰减为60 dB,通带内纹波小于0.2 dB.通过Multisim2001对该设计进行的仿真表明:该方法幅频特性好,并具有快速的衰减性.     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

应用于多模接收机的低功耗可编程增益放大器

针对多模接收机的应用,提出了引入一条闭环伪通路技术结构的可编程增益放大器,在保持一定的线性度及噪声性能的基础上,以较低的功耗实现较大的带宽.该电路增益步长为2 dB,增益变化范围1～39 dB.电路中内嵌了直流失调消除模块防止直流漂移引起的阻塞.芯片采用SMIC 0.13 μm 1P8M RF CMOS工艺实现.测试结...     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A novel zero dead zone PFD and efficient CP for PLL applications

This paper presents a high dynamic range programmable gain amplifier (PGA) with linear-in-dB and digital to analog converter (DAC) gain control using a BiCMOS process. The proposed PGA is composed of a folded Gilbert variable gain amplifier cell, a DC offset cancellation circuitry, two inductorless fixed gain amplifiers with bandwidth extension, a symmetrical exponential voltage generator, a novel buffer amplifier with active inductive peaking for testing purposes and a 10 bit R-2R DAC. The linear-in-dB and DAC gain control scheme facilitate the analog baseband gain tuning accuracy and stability, which also provides an efficient way for digital baseband automatic gain control. The PGA chip is fabricated using 0.13 μm SiGe BiCMOS technology. With a power consumption of 80 mA@1.2 V supply voltage, the fabricated circuit exhibits a tunable gain range of ? 30–27 dB (DAC linear gain step guaranteed), a 3 dB bandwidth of around 3.5 GHz and a gain resolution of better than 0.07 dB.     

A low power high linearity baseband for a direct conversation CMMB tuner

An analog baseband circuit made in a 0.35-μm SiGe BiCMOS process is presented for China Multimedia Mobile Broadcasting (CMMB) direct conversion receivers. A high linearity 8th-order Chebyshev low pass filter (LPF) with accurate calibration system is used. Measurement results show that the filter provides 0.5-dB passband ripple, 4% bandwidth accuracy, and -35-dB attenuation at 6 MHz with a cutoff frequency of 4 MHz. The current steering type variable gain amplifier (VGA) achieves more than 40-dB gain range with excellent temperature compensation. This tuner baseband achieves an OIP3 of 25.5 dBm, dissipates 16.4 mA under a 2.8-V supply and occupies 1.1 mm2 of die size.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35 μm CMOS is presented.The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF).The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications.In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide-10 to +40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA,and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.     

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning...     

一种具有精确增益控制的CMOS可编程增益放大器

采用0.13μm RF CMOS工艺,设计了一款具有精确增益步长控制的宽带可编程增益放大器.在传统电阻网络衰减器的基础上,提出了一种新的增益控制方法.该方法采用两个互相重叠的反馈环路,通过改变环路中跨导的比值以实现精细的增益步长控制.测试结果表明,当电源电压为1.2V时,功耗为24 mW,-3 dB带宽为600MHz....     

一种Doppler/FMCW双模式雷达模拟基带设计

基于55 nm CMOS工艺,设计了一种应用于24 GHz Doppler/ FMCW双模式雷达系统的模拟基带电路(ABB)。低通滤波器由两个改进型Tow-Thomas二阶节级联而成,实现了增益和带宽独立调节。采用一种基于7 bit可编程电流型数模转换器(IDAC)的两步逐次逼近型直流失调消除电路(SAR DCOC),可在Doppler模式10~600 Hz极低中频条件下,对混频器输出和基带自身直流失调进行消除。在IDAC和两级运放中混合使用BJT管,减小闪烁噪声,获得良好的低频噪声性能。后仿真结果表明,在2.5 V电源电压、模拟基带消耗电流4.9 mA下,两种模式增益范围均为6~62 dB,最大线性输入幅度(IP 1 dB)为10 dBm;62 dB增益时,Doppler模式、FMCW模式下的噪声系数分别小于42 dB、27 dB。蒙特卡罗仿真结果表明,当输入存在400 mV、200 mV直流失调时,基带输出直流失调仅为21.3 mV和16.4 mV。