Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs. This work was supported by the project PENED ’99 ED501 funded by GSRT of the Greek Ministry of Development, and the project PRENED ’99 KE 874 funded by the Research Committee of the Democritus University of Thrace. This work was partially sponsored by a scholarship from the Public Benefit Foundation of Alexander S. Onassis (Minas Dasygenis). Nikolaos Kroupis was born in Trikala in 1976. He receiver the engineering degree and Ms.C. degree in Department of Electrical and Computer Engineering from Democritous University of Thrace, Greece, in 2000 and 2002, respectively. Since 2002 he has been a Ph.D. student at the Laboratory of Electrical and Electronic Materials Technology. His research interests are in software/hardware co-design of embedded system for signal processing applications. Nikos D. Zervas received a Diploma in Electrical & Computer Engineering from University of Patras, Greece in 1997. He received the Ph.D. degree in the Department of Electrical and Computer Engineering of the same University in 2004. His research interests are in the area of high-level, power optimization techniques and methodologies for multimedia and telecommunication applications. He has received an award from IEEE Computer Society in the context of Low-Power Design Contest of 2000 IEEE Computer Elements Mesa Workshop. Mr. Zervas is a member of the IEEE, ACM and of the Technical Chamber of Greece. Minas Dasygenis was born in Thessaloniki in 1976. He received his Diploma in Electrical and Computer Engineering in 1999, from the Democritus University of Thrace, Greece, and for his diploma Thesis he was honored by The Technical Chamber of Greece and Ericsson Hellas. In 2005, he received his PhD Degree from the Democritus University of Thrace. His research interests include low-power VLSI design of arithmetic circuits, residue number system, embedded architectures, DSPs, hardware/ software codesign and IT security. He has published more than 20 papers in international journals and conferences and he has been a principal researcher in three European research projects. Konstantinos Tatas received his degree in Electrical and Computer Engineering from the Democritus University of Thrace, Greece in 1999. He received his Ph.D. in the VLSI Design and Testing Center in the same University by June 2005. He has been employed as an RTL designer in INTRACOM SA, Greece between 2000 and 2003. His research interests include low-power VLSI design of DSP and multimedia systems, computer arithmetic, IP core design and design for reuse. Antonios Argyriou received the degree in Electrical and Computer engineering from the Democritous University of Thrace, Greece, in 2001, and the M.S. and Ph.D. degrees in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, in 2003 and 2005, respectively. His primary research interests include wireless networks, mobile computing and multimedia communications. He is a member of the IEEE and ACM. Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He is currently working as Ass. Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Greece. His research interests include low power design, parallel architectures, embedded systems design, and VLSI signal processing. He has published more than 140 papers in international journals and conferences. He was leader and principal investigator in numerous research projects funded from the Greek Government and Industry as well as the European Commission (ESPRIT II-III-IV and 5th and 6th IST). He has served as General Chair and Program Chair for the International Workshop on Power and Timing Modelling, Optimisation, and Simulation (PATMOS). He received an award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT IV). He is a member of the IEEE, the VLSI Systems and Applications Technical Committee of IEEE CAS and the ACM. Antonios Thanailakis was born in Greece on August 5, 1940. He received B.Sc. degrees in physics and electrical engineering from the University of Thessaloniki, Greece, 1964 and 1968, respectively, and the Msc. and Ph.D. Degrees in electrical engineering and electronics from UMIST, Manchester, U.K. in 1968 and 1971, respectively. He has been a Professor of Microelectronics in Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece, since 1977. He has been active in electronic device and VLSI system design research since 1968. His current research activities include microelectronic devices and VLSI systems design. He has published a great number of scientific and technical papers, as well as five textbooks. He was leader for carrying out research and development projects funded by Greece, EU, or other organizations on various topics of Microlectronics and VLSI Systems Design (e.g. NATO, ESPRIT, ACTS, STRIDE).     

An Algorithm for Adaptive Mean Filtering and Its Hardware Implementation

Noise due to the sensor and the electronics of a camera is an undesirable issue in any machine vision application. Such noise tends to corrupt images and to obstruct any further analysis. An algorithm to detect and cancel such noise, using statistical methods, is presented in this paper. The proposed algorithm is an adaptive mean filter, which filters out image regions that are found to be noise corrupted. The efficiency of the proposed filter was examined both qualitatively and quantitatively, by software simulation in several noisy conditions. The main advantage of the filter in hand is that it is appropriate for hardware implementation and can be easily incorporated to smart cameras. The hardware implementation of the filter is also presented in this paper. This implementation aims at time critical applications such as machine vision, inspection and visual surveillance. Ioannis Gasteratos holds a Diploma in Electrical Engineering from the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece, 2004. His research interests include digital VLSI design, computer architectures and artificial intelligence. He is a member of the IEEE, and a member of the Technical Chamber of Greece (TEE). Antonios Gasteratos is a Lecturer of Robotics in the Department of Production and Management, Democritus University of Thrace, Greece. He holds a PhD from the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece, 1999. During 2001–2003 he was a visiting Assistant Professor in the Department of Electrical and Computer Engineering, Democritus Univesrsity of Thrace. He serves as a reviewer to numerous of Scientific Journals and International Conferences. His research interests are mainly in computer and robot vision and sensory data fusion. He is a member of the IEEE, the IAPR, the EURASIP, the Hellenic Society of Artificial Intelligence (SETN) and the Technical Chamber of Greece (TEE). Ioannis Andreadis received the Diploma Degree from the Department of Electrical & Computer Engineering, DUTH, Greece, in 1983 and the MSc and PhD Degrees from the University of Manchester Institute of Science & Technology, UK, in 1985 and 1989, respectively. His research interests are mainly in Intelligent Systems, Machine Vision and VLSI based computing architectures. He joined the Department of Electrical & Computer Engineering, DUTH in 1993. He is a member of the Editorial Board of the Pattern Recognition Journal, TEE and IEEE.     

An Efficient Dictionary Organization for Maximum Diagnosis

The major problem of fault diagnosis with a fault dictionary is the enormous amount of data. The technique used to manage this data can have a significant effect on the outcome of the fault diagnosis procedure. If information is removed from a fault dictionary in order to reduce the size of the dictionary, its ability to diagnose stuck-at faults and unmodeled faults may be severely debased. Therefore, we focus on methods for producing a dictionary that is both small and lossless-compacted. We propose an efficient dictionary for maximum diagnosis, which is called SD-Dictionary. This dictionary consists of a static sub-dictionary and a dynamic sub-dictionary in order to make a smaller dictionary while maintaining the critical information needed for the diagnostic ability. Experimental results on ISCAS’ 85, ISCAS’ 89 and ITC’ 99 benchmark circuits show that the size of the proposed dictionary is substantially reduced, while the dictionary retains most or all of the diagnostic capability of the full dictionary. This work was supported by the “System IC 2010” project of Korea Ministry of Science and Technology and Ministry of Commerce, Industry and Energy. Editor: Y. Takamatsu Sunghoon Chun received the B.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 2002. He was a Reseach Engineer with ASIC Research Center in Yonsei University. He researched for test methodologies for SoC. He received the M.S. degrees in Electrical and Electronic Engineering from Yonsei University in 2005. He is currently working toward Ph.D. degree in Electrical and Electronic Engineering at Yonsei University. His area of interests includes SoC testing, delay testing, fault diagnosis, functional testing for processor based system and test methodologies for signal integrity faults. Sangwook Kim received the B.S., and M.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 1999, and 2001, respectively. He researched for Digital Signal Processor design and fault diagnosis of VLSI. He is a Research Engineer with SoC Design Group of System IC Division in LG Electronics, Inc. He is currently interested in SoC design for HDTV and design verification. Hong-Sik Kim was born in Seoul, Korea, on April 4, 1973. He received the B.S., M.S. and Ph.D. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 1977, 1999, and 2004, respectively. He was a Post-Doctorial Fellow with the Institute of Virginia Technology. He is currently working on System LSI Group in the Samsung Electronics. His current research interest includes design-for-testability, built-in self tests and fault diagnosis. Sungho Kang received the B.S. degree from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin. He was a Post-Doctorial Fellow with the University of Texas at Austin, a Research Scientist with the Schlumberger Laboratory for Computer Science, Schlumberger Inc., and a Senior Staff Engineer with the Semiconductor Systems Design Technology, Motorola Inc. Since 1994, he has been an Associate Professor with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea. His current research interests include VLSI design, VLSI CAD and VLSI testing and design for testability.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Analog Circuit Synthesis Using Linear and Nonlinear Current Amplifiers

Various design techniques are presented for obtaining current-mode filters suitable for operation at high frequencies. For this purpose CMOS and or bipolar current amplifiers are used as active building blocks. The derived circuits simulate LC passive prototype filters. Second order resonators can also be obtained by following the same techniques. The presented circuits are modular in structure, thus, their electronic and layout design is very easy. Low-voltage, low-power design is also feasible. Simulation examples for all-pole filters and filters with transmission zeros are given. George Souliotis received the B.Sc. degree in physics from the University of Ioannina, Ioannina, Greece, in 1993 and the M.Sc. and Ph.D. degrees in electronics from the University of Patras, Patras, Greece, in 1998 and 2003, respectively. From 2000 to 2002, he was with Giga Hellas, an Intel company, designing high-speed electronic circuits for transceivers for optical networks. He is co-inventor of a patent that was developed through that work. He is currently a Post-Doctoral Researcher with the Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece. His research interests include analog and mixed signal integrated circuits for high-speed communication applications, current mode circuits, continuous time active filters and CMOS-BiCMOS VLSI design. Nikos Fragoulis was born in Megara Attikis, Greece, in 1972. He received the B.S. degree in physics and the M.Sc. degree in electronics and Ph.D. in electronics from the Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece, in 1995, 1998 and 2005 respectively. He is currently a post-doctoral researcher with the Electronics Laboratory, Department of Physics, University of Patras, Patras Greece. His research interests include, continuous time filtering, and analog integrated circuits for broadband telecommunication applications. Ioannis Haritantis received the Ph.D. in Electronics, in 1976, from the Physics Department, University of Patras, Patras, Greece, in collaboration with the Electrical Engineering Department, Imperial College, London, UK. For many years he has conducted scientific research on the development and design of circuits, discrete component and/or integrated, which are suitable for analog signal processing. His other fields of interest include, network theory, design and testing of integrated circuits, integrated active devices for telecommunications and medical instrumentation, smart sensors, and e-learning. During the past few years his focus is on the design of low-power, low-voltage, tunable, integrated active filters of high dynamic range that could operate at high frequencies. Professor Haritantis in now the director of the Electronics Laboratory, Division of Electronics and Computers, Department of Physics, University of Patras, Patras, Greece. He is also in the editorial board of the journal “Analog Integrated Circuits and Signal Processing”, Kluwer Academic Publishers.     

Characteristic Investigation of New Pathological Elements

A characteristic investigation of the new pathological elements (i.e voltage mirror and current mirror) has been presented. Many nullor-mirror equivalences are explored. The circuit cascadability is discussed with nullor and mirror concepts. Also, the conventional inverse network transformation has been extended for applying to the circuits with current mirror output. To demonstrate the use of presented properties, practical examples have been given. The derived circuits have been verified with HSPICE simulation and the simulation results confirm with our theoretical prediction.Hung-Yu Wang was born in Kaohsiung, Taiwan, Republic of China, on January 4, 1969. He received the Ph.D. degree in optical sciences from National Central University, Chung-Li, Taiwan in 2002.Since 1993 he has worked on promoting the prototyping IC implementation of academic researches, and propelling the collaboration of the academia and industries in Chip Implementation Center (CIC), National Science Council of the Republic of China. In 2003 he became a researcher and the deputy director in Division of Chip Implementation Service of CIC. He is currently working on South Region Office of National Chip Implementation Center, National Applied Research Laboratories as a researcher and the department manager. His research interests are in current-mode circuits design, analog IC design and analog IP design.Ching-Ting Lee was born in Taoyuan, Taiwan, R.O.C., on November 1, 1949. He received his B.S. and M.S. in Electrical Engineering Department of the National Cheng-Kung University, Taiwan, in 1972 and 1974, respectively. He received Ph.D. degree in Electrical Engineering Department from the Carnegie-Mellon University, Pittsburgh, PA, in 1982.He worked on Chung Shan Institute of Science and Technology, before he joined the Institute of Optical Sciences, National Central University, Chung-Li, Taiwan, as a Professor in 1990. He works on National Cheng-Kung University as the dean of Electrical Engineering and Computer Science and the professor or the Institute of Microelectronics, Department of Electrical Engineering in 2003. His current research interests include theory, design, and application of guided-wave structures and devices for integrated optics and waveguide lasers. His research activities have also involved in the research concerning semiconductor lasers, photodetectors and high-speed electronic devices, and their associated integration for electrooptical integrated circuits. He received the outstanding Research Professor Fellowship from the National Science Council (NSC), R.O.C. in 2000 and 2002. He also received the Optical Engineering Medal from Optical Engineering Society and Distinguish Electrical Engineering professor award from Chinese Institute of Electrical Engineering Society in 2003.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of Department of Electronic Engineering. His biography is included in the 7th Edition (2003–2004) of Who’s Who in Science and Engineering.His current researches include current-mode circuits design, VLSI design, analog IC design and analog IP design.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Resource management of IP-enabled DVB-T networks in the context of wireless B3G systems

The wireless beyond 3G systems or the so called Composite Radio Environments (CRE) (or even 4G systems), consist of multiple type radio access technologies, collaborating with each other, providing both diverse access alternatives and QoS improvement, especially as far as concerns protection against traffic congestion and loss of radio coverage situations. The merits deriving from beyond 3G systems interest not only network and service providers but also the mobile users. Additionally, the need of broadband wireless access is directly associated with the intense demand for IP multimedia services (e.g. video streaming or high speed web browsing), mainly inside hot-spot areas. Taking into consideration the above described tendency in the area of wireless network systems, the IP-enabled DVB-T (the terrestrial specification of the Digital Video Broadcasting family) systems appear as an attractive alternative network access in the CRE context. Along this direction, this paper presents the most important aspects of a CRE network management system (NMS), focusing on the component responsible for the DVB-T resource management (RM). Finally, we implement and investigate through simulation a greedy algorithm suitable for DVB-T networks that performs fast resource management and configuration. We also provide some indicative results which prove that the algorithm demonstrates a close to optimal performance at the RM functionality. This work is partially funded by the Commission of the European Communities, under the Fifth Framework Program, within the IST project CREDO (Composite Radio for Enhanced Service Delivery during the Olympics). Dimitris Kouis is currently a research associate at the Electrical Engineers School of the National Technical University of Athens, in Greece. He received his diploma from the Computer Engineering and Informatics department of the Polytechnic School of the University of Patras and a Ph.D. degree in Telecommunications and Computing from the National Technical University of Athens, Greece, in 1999 and 2005 respectively. He has worked in research projects in the context of the IST framework. His research interests include mobile and wireless networking, wireless network resources optimization techniques and large-scale software platforms. He is a member of the Technical Chamber of Greece since 1999. Panagiotis Demestichas received the Diploma and the Ph.D. degrees in Electrical and Computer Engineering from the National Technical University of Athens (NTUA). From September 2002 he is an Assistant Professor at the University of Piraeus, in the department of Technology Education and Digital Systems. From 1993 until August 2002 he has been a senior research engineer with the Telecommunications Laboratory in NTUA. From February 2001 until August 2002 he was a lecturer at NTUA, in the department of Applied Mathematics and Physics, teaching courses on programming languages, data structures, data bases, telecommunications. From September 2000 until August 2002 he taught telecommunication courses, in the department of Electronics of the Technological Education Institute of Piraeus. Most of his current activities focus on the FP6/IST project E2R (End-to-End Reconfigurability). He is also the chairman of Working Group 6 (WG6), titled Reconfigurability, of the Wireless Word Research Forum (WWRF). At the international level he has actively participated in the projects IST MONASIDRE Management of Networks and Services in a Diversified Radio Environment), where he was the project manager, as well as other EU projects under the IST, ACTS, RACE II, EURET, BRITE/EURAM frameworks. His research interests include the design, management and performance evaluation of mobile and broadband networks, service and software engineering, algorithms and complexity theory, and queueing theory. He has authored over 100 publications in these areas in international journals and refereed conferences. He is a member of the IEEE, ACM and the Technical Chamber of Greece. George Koundourakis was born in Alex/polis, Greece, in 1979. He received the degree of Electrical and Computer Engineer from the National Technical University of Athens (NTUA), Greece, in July 2001. He is a Research Associate and PhD candidate at the Telecommunications Laboratory of the Division of Communication, Electronic and Information Engineering at NTUA. He has worked in research projects in the context of the IST framework. He is the author of several scientific papers in the areas of mobile communications. He is a member of the Technical Chamber of Greece. Michael E. Theologou received the degree in Electrical Engineering from Patras University and his Ph.D. degree from the School of Electrical Engineering and Computer Science of the National Technical University of Athens (NTUA). Currently he is a Professor in the School of Electrical Engineering and Computer Science of NTUA. His research interests are in the field of Mobile and Personal communications. He has many publications in the above areas. Dr Theologou is a member of IEEE and the Technical Chamber of Greece.     

Systematic Synthesis of Active-RC Circuit Building-Blocks

In this paper, we show how some basic building blocks for active-RC circuit design, such as amplifiers, impedance converters and simulated inductance circuits, may be synthesised in a systematic way by expansion of their port admittance matrices. The circuit topology emerges from the synthesis procedure, allowing all possible implementations to be identified and explored. Nullors representing ideal op-amps and transistors are represented within the nodal admittance matrix of a synthesised circuit by linked infinity parameters. In nodal admittance matrices describing ideal circuits synthesised, the replacement of linked infinity parameters by finite parameters provides a seamless transition to non-ideal analysis and practical circuit design.Now with the Singaporean Armed Services.David Haigh was born in Middlesex, England, in 1946. He obtained the B.Sc. degree in Electrical Engineering from Bristol University in 1968 and in 1976 he received the Ph.D. degree from the University of London. From 1968 until 1972 he worked under Dr. Wolja Saraga first at the GEC Hirst Research Centre and then, from 1972, at Imperial College London where he worked on microelectronic high precision filters. In 1987 he joined the staff of the Electronic and Electrical Engineering Department of University College London, where he studied analogue integrated circuit design with particularly interest in high frequency circuits. In 2003 he re-joined the Department of Electrical and Electronic Engineering at Imperial College London, where his interests broadened to include general approaches for analogue circuit synthesis. He is editor-in-chief (Europe) of the Analog Integrated Circuits and Signal Processing Journal.Fang Qun Tan graduated with a B.Eng. degree from Imperial College London in 2002. He then studied for the M.Sc. in Analogue and Digital integrated Circuit Design at Imperial College and graduated with distinction in 2003. His M.Sc. project was on the subject of systematic synthesis methods for analogue circuits. At present Fang Qun is with the Singapore Armed Services.Christos Papavassiliou was born in Athens, Greece, in 1960. He received the B.Sc. degree in physics from the Massachusetts Institute of Technology and the Ph.D. degree in Applied Physics from Yale University. He has worked on monolithic microwave integrated circuit (MMIC) design and measurements at FORTH in Crete, Greece, and has been involved in several European and regional projects on GaAs MMIC technology. In 1996 he joined Imperial College London, where he is currently a Senior Lecturer. He currently works on SiGe technology development as well as instrumentation and substrate noise coupling in mixed mode integrated circuit design. He has 30 publications.     

FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 μ m CMOS technology at a supply voltage of ±0.75 V. A part of this paper has appeared in IEEE APCCAS 2002 and NSM 2003. S. Sharma was born on 6th July 1967 at village Bhagta, district Udhampur, J and K (India). He received MSc Physics (Electronics) degree from University of Jammu in 1991 and was awarded University Gold Medal. After qualifying NET (CSIR), he joined as Lecturer in 1995 in the department of Physics and Electronics of the same University. He is presently a Senior Lecturer and pursuing for Ph.D. degree in the area of Analog Integrated Circuits. He has eight papers published in National/International Conferences/Journals. He is a life member of IETE (India). S.S. Rajput was born on July 1, 1957, at village Bashir Pur, District Bijnor UP India. He received his B. E. in Electronics and Communication Engineering and M. E. in Solid State Electronics Engineering from University of Roorkee, Roorkee, India (Now IIT, Roorkee) in 1978 and 1981 respectively and was awarded University gold medal in 1981. He earned his Ph.D. degree from Indian Institute of Technology, Delhi in 2002 and his topic of research was “Low voltage current mode analog circuit structures and their applications”. He joined National Physical Laboratory, New Delhi, India as Scientist B in 1983, where he is presently serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include low voltage analog VLSI, instrument design for space applications, Digital Signal Processing, Fault tolerant design, and fault detection. He has chaired the many sessions in Indian as well as International conferences. He is Fellow member of IETE (India). He has been awarded best paper award for IETE Journal of Education for the year 2002. He has delivered many invited talks on Low Voltage Analog VLSI. Few tutorials have been presented in International Conferences on his Research Work. He has more than 30 publications in national and international journals. L.K. Mangotra was born on 14th April 1944 at Jammu, India. He received M.Sc. (Physics) from University of Kashmir in 1968 and Ph.D. (High Energy Physics) from University of Jammu in 1974. He worked as Assistant Director in Forensic Laboratory of J and K Govt. from 1974–78. He joined Physics Department, University of Jammu as Lecturer in 1978 and became Professor in 1988. He has 131 publications in International Journals and 41 papers in proceedings of International/National Conferences. He has number of visits to foreign Universities in connection with research and has been awarded various Fellowships. He is a member of various Professional/Academic/Administrative bodies. Presently, Prof. Mangotra is an Advisor to University of Jammu for Modernization of University Infrastructure and Principal Investigator for Jammu University and Coordinator of All India Universities in the International Collaborative research project “ALICE” in High Energy Physics sponsored by Department of Atomic Energy and Department of Science and Technology, Govt. of India. S.S. Jamuar was born on 27th November 1949. He received his BSc. Engineering Degree in Electronics and Communication from Bihar Institute of Technology, Sindri in 1967, M. Tech and Ph.D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined department of Electrical Engineering of IIT Delhi in 1977, where he became Professor in 1991. He is presently Professor in the department of Electrical and Electronic Engineering Department, Faculty of Engineering, University Putra Malaysia, Malaysia. His area of research interest includes Electronic Circuit Design, Instrumentation and Communication systems. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999. Dr. Jamuar is senior member of IEEE and Fellow member of IETE (India). He is presently the Chair for CASS Chapter of IEEE Malaysia Section.     

VHDL Implementation of the Fast Wavelet Transform

In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two-channel subband coder, is described. The units were simulated, synthesized, and optimized using Mentor^? design tools. The final design was verified with VHDL test benches and Matlab image processing tools. Results of the decomposition for color images validate the design. Utilizing a clock frequency of 25 MHz, a time period of 45 ms was estimated for the decomposition process of a 640 × 480 color image, which makes it feasible for real time video compression. The size of the layout was found to be within 2.5 × 2.5 mm, which suggests a 40 pin-package tiny frame. Paul Salama received the B.Sc. in Electrical Engineering (First Class Honors) from the University of Khartoum in 1991, and the M.S.E.E. and the Ph.D. degrees from Purdue University in 1993 and 1999, respectively. He is currently an Associate Professor at the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI). His research interests include image and video compression, image processing, Transmission of compressed Video, Ill posed problems, and medical imaging. Dr. Salama is a member of SPIE, Tau Beta Pi, and Eta Kappa Nu. Maher E. Rizkalla received his Ph.D. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1985. From Jan. 1985 to Sep. 1986, he was a Visiting Scientist at Argonne National Laboratory, Argonne, IL while being a Visiting Assistant Professor at Purdue University Calumet. Since 1986 he has been with the Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis (IUPUI), where he is Professor of Electrical and Computer Engineering. His research interests include solid-state electronics, VLSI design as applied to DSP, electromagnetics, and engineering education. He has published over 100 papers in these areas. He received the outstanding teaching awards in the ECE Department and in the School five times and was the Professor of the Year at Purdue Calumet in 1986. He is the recipient of one NSF grant, and two FIPSE grants, and is COPI of a number of industrial and equipment grants. Dr. Rizkalla is a Senior Member, IEEE, and a Professional Engineer (PE) registered in the State of Indiana. Michael Eckbauer received the M.S.E.E. degree in Electrical Engineering from Indiana University Purdue University Indianapolis (IUPUI) in December 2002. He is currently with GE Medical Systems in Waukesha, Wisconsin.     

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current

In recent years, Defect Oriented Testing (DOT) has been investigated as an alternative testing method for analog circuits. In this paper, we propose a wavelet transform based dynamic supply current (IDD) analysis technique for detecting catastrophic and parametric faults in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike Fourier transform which decomposes a signal in frequency components only. Simulation results on benchmark circuits show that wavelet transform has higher fault detection sensitivity than Fourier or time-domain methods and hence, can be considered very promising for defect oriented testing of analog circuits. Effectiveness of wavelet transform based DOT amidst process variation and measurement noise is studied.This research is supported in part by MARCO GSRC under contract number SA3273JB.A paper based on this work was presented at the Fourth IEEE Latin American Test Workshop, Natal, Brazil, February 2003.Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Masters degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN.He has worked in the EDA industry on RTL synthesis and verification since 2000. His research interest includes defect-based testing, diagnosis, noise analysis, and noise-aware design.Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN.He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings—Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).     

Reduced-Complexity Iterative Multiuser Detection for DS-CDMA

A reduced-complexity iterative multiuser detection scheme is proposed. The scheme involves a simple way of choosing only K + 1 user bit vectors instead of the full-complexity 2^K for the likelihood computation, thus reducing the complexity to O(K). An alternative, reduced computation method of increasing this list of vectors after each iteration is also presented. Simulations over AWGN, imperfect power control and multipath conditions demonstrate that the performance of the proposed reduced-complexity method is close to that of the full-complexity.Ju Yan Pan received the B.S.E.E. degree from Mississippi State University, U.S.A., in 1998 and the M.Eng. degree from Nanyang Technological University, Singapore, in 2002. He is currently working as a system design engineer at the wireless communication technology department of Oki Techno Centre Pte. Ltd. in Singapore Science Park II. His current reserach interests include third-generation WCDMA systems, turbo decoding and multiuser detection.Cheong Boon Soh received the Bachelor of Engineering in Electrical and Computer Systems Engineering (Hons I) and Ph.D. degrees from Monash University, Victoria, Australia, in 1983 and 1987, respectively. He is an Associate Professor in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. He has published more than one hundred international journal papers. His current research interests are robust control, system theory, nonlinear systems, coding theory, mobile communication systems and intelligent systems.Gunawan Erry received his B.Sc degree in Electrical and Electronic Engineering from the University of Leeds, U.K., in 1983. He then received his MBA and Ph.D. in total technology from Bradford University in 1984 and 1988 respectively. From 1984 to 1988, he worked for Communication Systems Research Ltd, U.K. as a satellite communication systems engineer. In 1988, he moved to Space Communications (SAT-TEL) Ltd, U.K. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore in 1989. Currently, he is an Associate Professor in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. His current research interests are in digital communications, mobile and satellite communications, error coding and spread-spectrum. He has published over sixty international research papers and has been a consultant to a local company on the study of DECT system and Bluetooth.     

Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System

This paper presents the idea of managing the comprising computations of an application performed by an embedded networked system. An efficient algorithm for exploiting the timing slack of building blocks of the application is proposed. The slack of blocks can be utilized by replacing them with slower but cheaper, i.e. better, modules and by assigning the computations to the proper resources. Thus, our approach manages the comprising computations and system resources and can indirectly assist the realtime scheduling of computations on system resources. This is performed without compromising the timing constraints of the application and can lead to significant improvements in power dissipation, computation accuracy or other metrics of the application domain. Our algorithm is well-suited for arbitrary tree computations. Moreover, it delivers solutions that are desirably close to the optimal solution. Experimental results for a number of object tracking applications implemented in an networked system with embedded computation resources, exhibit a significant amount of slack utilization. Soheil Ghiasi received his B.S. from Sharif University of Technology, Tehran, Iran in 1998, and his M.S. and Ph.D. in Computer Science from the University of California, Los Angeles in 2002 and 2004, respectively. Currently, he is an assistant professor in the department of electrical and computer engineering at the University of California, Davis. His research interests include different aspects of Embedded and Reconfigurable system design. Elaheh Bozorgzadeh received the B.S. degree in Electrical Engineering from Sharif University of Technology, Iran in 1998, M.S. degree in Computer Engineering from Northwestern University in 2000, and Ph.D. degree in Computer Science from the University of California, Los Angeles, in 2003. She is currently as assistant professor in the Department of Computer Science at the University of California, Irvine. Her research interest includes VLSI CAD, design automation for embedded systems, and reconfigurable computing. She is a member of ACM and IEEE. Karlene Nguyen received her B.S. and M.S. from University of California, Los Angeles in 2001 and 2003, respectively. She has been working with Prof. Majid Sarrafzadeh for her M.S. degree. Her research interests include embedded hardware and software design. Majid Sarrafzadeh received his B.S., M.S. and Ph.D. in 1982, 1984, and 1987 respectively from the University of Illinois at Urbana-Champaign in Electrical and Computer Engineering. He joined Northwestern University as an Assistant Professor in 1987. In 2000, he joined the Computer Science Department at University of California at Los Angeles (UCLA). His recent research interests lie in the area of Embedded and Reconfigurable Computing, VLSI CAD, and design and analysis of algorithms. Dr. Sarrafzadeh is a Fellow of IEEE for his contribution to “Theory and Practice of VLSI Design.” He received an NSF Engineering Initiation award, two distinguished paper awards in ICCAD, and the best paper award in DAC. He has served on the technical program committee of numerous conferences in the area of VLSI Design and CAD, including ICCAD, DAC, EDAC, ISPD, FPGA, and DesignCon. He has served as committee chairs of a number of these conferences. He is on the executive committee/steering committee of several conferences such as ICCAD, ISPD, and ISQED. He is the program committee chair of ICCAD 2004. Professor Sarrafzadeh has published approximately 250 papers, is a co-editor of the book “Algorithmic Aspects of VLSI Layout” (1994 by World Scientific), and co-author of the book “An Introduction to VLSI Physical Design” (1996 by McGraw Hill). Dr. Sarrafzadeh is an Associate Editor of ACM Transaction on Design Automation (TODAES) and an Associate Editor of IEEE Transactions on Computer-Aided Design (TCAD) and ACM Transactions on design Automation (TODAES). Dr. Sarrafzadeh has collaborated with many industries in the past fifteen years including IBM, Motorola, and many CAD industries. He is the architect of the physical design subsystem of Monterey Design Systems main product. He is a co-founder of Hier Design, Inc.     

A CMOS Image Processing Sensor for the Detection of Image Features

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16 × 16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 μsec. Masatoshi Nishimura was born in 1962 in Japan. He received his B.S. degree in mathematical engineering and information physics from the University of Tokyo in 1984. In 2001 he received his Ph.D. in Electrical Engineering from the University of Pennsylvania. His Ph.D. research focused on biologically inspired algorithms for the feature detection in visual images. Except for the three years he spent at University of Pennsylvania, he has been working for Sankyo since 1984, where he has been involved in the research and development of medical instruments including a microchip for capillary electrophoresis. He is currently working in the field of bioinformatics. Jan Van der Spiegel received his Masters and Ph.D. degrees in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. He joined the University of Pennsylvania in 1981 where he is currently a Professor of Electrical and Systems Engineering and the director of the Center for Sensor Technologies. He was the chairman of the Department of Electrical Engineering from 1998 to 2002 and the interim chairman of the Electrical and Systems Engineering department at the University of Pennsylvania from 2002 to 2004. His research interests are in mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters. He is the author of over 150 journal and conference papers and holds 4 patents. He is a Fellow of the IEEE (2002) and the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching. He was also Editor of Sensors and Actuators A for North and South America from 1983 to 2004.     

Modeling of Block-Based DSP Systems

Modeling semantics based on dataflow graphs are used widely in design tools for digital signal processing (DSP). This paper develops efficient techniques for representing and manipulating block-based operations in dataflow-based DSP design tools. In this context, a block refers to a finite-length sequence of data items, such as a sequence of speech samples, an image, or a group of video frames, as part of an enclosing data stream. We develop in this paper a meta-modeling technique called blocked dataflow (BLDF) for augmenting DSP design tools with more effective blocked data support in an efficient and general manner. We compare BLDF against alternative modeling approaches through a detailed case study of an MPEG 2 video encoder system.Dong-Ik Ko received the B.S. and M.S. degree from Korea University, Korea, in 1993 and in 1995, all in electrical and computer engineering. He had been with LG Electronics, Korea as an embedded system develpoer from 1996 to 2001.He is now a Ph.D. student of Electrical and Compuetr Engineering, University of Maryland College Park, MD. His resarch interests include hardware/software co-design, design methodology for embedded systems, and performance and memory issues in system-level synthesis.Shuvra S. Bhattacharyya is an associate professor in the Department of Electrical and Computer Engineering, and the Institute for Advanced Computer Studies (UMIACS) at the University of Maryland, College Park. He is also an affiliate associate professor in the Department of Computer Science. Dr. Bhattacharyya is coauthor or coeditor of three books and the author or coauthor of more than 70 refereed technical articles. His research interests include VLSI signal processing, embedded software, and hardware/software co-design. He received the B.S. degree from the University of Wisconsin at Madison, and the Ph.D. degree from the University of California at Berkeley. Dr. Bhattacharyya has held industrial positions as a Researcher at the Hitachi America (San Jose, California) Semiconductor Research Laboratory, and as a Compiler Developer at Kuck & Associates (Champaign, Illinois).     

1.1 V Low-Power ΣΔ Modulator for 14-bit, 16 KHz A/D Conversion Using a New Low-Voltage Class-AB Op-amp

This paper presents the implementation of a second order modulator for a 1.1 V supply voltage. A new class-AB CMOS operational amplifier has been designed in order to achieve high-resolution under very-low-voltage operation. The modulator has been implemented using a 0.35 m CMOS technology with 0.65 V transistor threshold voltage. Experimental results show 14 bits of resolution over 16 kHz nyquist rate with an oversampling ratio of 160.Fernando Muñoz Chavero was born in El Saucejo, Sevilla, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2002, respectively. Since 1997, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1999). His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing.Alfredo Pérez Vega-Leal was born in Seville, Spain. He received the Telecommunications Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2003, respectively. Since 1995, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an Associate Professor in 1999. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion.Ramón González Carvajal was born in Seville, Spain. He received the Electrical Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1995 and 1999, respectively. Since 1996, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1996), and Professor (2002). He has published more than 100 papers in International Journals and Conferences. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing.Antonio Torralba was born in Seville, Spain. He received the electrical engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1983 and 1985, respectively. Since 1983, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Assistant professor, Associate Professor (1987), and Professor (1996). He has published 30 papers in journals and more than 80 papers in conferences. His research interests are in the design and modeling of low-voltage analog circuits, analog and mixed-signal design, analog to digital conversion, and electronic circuits and systems with application to control and communication.Jonathan Noel Tombs was born in Oxford, UK. He received the Electrical Engineering and Ph.D. degrees from Oxford University, UK, in 1987 and 1991, respectively. Since 1993, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1997), and Professor (2002). He has published more than 50 papers in International Journals and Conferences. His research interests are related to Digital Design and system verification with VHDL, low-voltage low-power analog circuit design, A/D and D/A conversion and analog and mixed signal processing.Jaime Ramírez-Angulo is currently Klipsch Distinguished Professor, IEEE fellow and Director of the Mixed-Signal VLSI lab at the Klipsch School of Electrical and Computer Engineering, New Mexico State University (Las Cruces, New Mexico), USA. He received a degree in Communications and Electronic Engineering (Professional degree), a M.S.E.E. from the National Polytechnic Institute in Mexico City and a Dr.-Ing. degree form the University of Stuttgart in Stuttgart, Germany in 1974, 1976 and 1982 respectively. He was professor at the National Institute for Astrophysics Optics and Electronics (INAOE) and at Texas A&M University. His research is related to various aspects of design and test of analog and mixed-signal Very Large Scale Integrated Circuits.     

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hard-ware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, in June 2000 and December 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Ching-Yeh Chen was born in Taipei, Taiwan, in 1980. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, in 2002. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His research interests include intelligent video signal processing, global/local motion estimation, scalable video coding, and associated VLSI architectures. Chen-Han Tsai received the B.S. degree in electrical engineering from National Taiwan University in 2002. Now he is working toward the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include face detection and recognition, motion estimation, H.264/AVC video coding, digital TV systems, and related VLSI architectures. Chun-Fu Shen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University in 1996 and 1998, respectively. After two years of military service, he joined VIVOTEK, Inc., Taipei County, Taiwan, in 2000. He developed many video coding systems and IP camera products on DSP platforms and ASICs. His major research interests include JPEG, H.263, MPEG-4, and H.264/AVC coding systems, network camera SOC, and embedded systems. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an instructor (1981–1986), and an associate professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an associate professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a visiting consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is a professor of National Taiwan University. From 2004, he is also the executive vice president and the general director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tau Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He was also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He has served as the associate editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, the associate editor of IEEE Transactions on VLSI Systems since 1999, the associate editor of Journal of Circuits, Systems, and Signal Processing since 1999, and the guest editor of Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology since 2001. Now he is also the associate editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing and the associate editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Awards from ROC Computer Society in 1990 and 1994. From 1991 to 2005, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Outstanding Research Award from National Science Council (NSC) and the Dragon Excellence Award from Acer. He was elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Medium Access Control for Integrated Multimedia Wireless Access with the Use of a Video Packet Discard Scheme

A well designed Medium Access Control (MAC) protocol for wireless networks should provide an efficient mechanism to share the limited bandwidth resources, and satisfy the diverse and usually contradictory Quality of Service (QoS) requirements of each traffic class. In this paper a new MAC protocol for next generation wireless communications is presented and investigated. The protocol uses a combined Packet Discard/Forward Error Correction scheme in order to efficiently integrate MPEG-4 videoconference packet traffic with voice, SMS data and web packet traffic over a noisy wireless channel of high capacity. Our scheme achieves high aggregate channel throughput in all cases of traffic load, while preserving the Quality of Service (QoS) requirements of each traffic type, and is shown to clearly outperform DPRMA, another efficient MAC protocol proposed in the literature for multimedia traffic integration over wireless networks. Dr. Polychronis Koutsakis was born in Hania, Greece, in 1974. He received his 5-year Diploma in Electrical Engineering in 1997 from the University of Patras, Greece and his MSc and Ph.D. degrees in Electronic and Computer Engineering in 1999 and 2002, respectively, from the Technical University of Crete, Greece. He was a Visiting Lecturer at the Electronic and Computer Engineering Department of the same University for three years (2003–2006). He is currently an Assistant Professor at the Electrical and Computer Engineering Department of McMaster University, Canada. His research interests focus on the design, modeling and performance evaluation of computer communication networks, and especially on the design and evaluation of multiple access schemes for multimedia integration over wireless networks, on call admission control and traffic policing schemes for both wireless and wired networks, on multiple access control protocols for mobile satellite networks, wireless sensor networks and powerline networks, and on traffic modeling. Dr. Koutsakis has authored more than 45 peer-reviewed papers in the above mentioned areas, has served as a Guest Editor for an issue of the ACM Mobile Computing and Communications Review, as a TPC member for conferences such as IEEE GLOBECOM, IEEE LCN and IEEE PerCom, will serve as Session Chair for the IEEE GLOBECOM 2006 Symposium on Satellite & Space Communications and serves as a reviewer for most of the major journal publications focused on his research field. Moisis Vafiadis was born in Elefsina, Greece, in 1980. He has recently completed his studies towards the Diploma in Electronic Engineering at the Technological Educational Institute of Crete, Greece. His research interests focus on wireless personal communication networks, and especially on the MAC layer and on the development and testing of wireless multimedia applications.     

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Todays digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.Alireza Shoa received his B.Sc degree in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 2001 and M.A.Sc degree in Electrical Engineering from McMaster University, Hamilton, Canada in 2003. Currently, he is a PhD candidate in Electrical Engineering at McMaster University. His research interests include VLSI circuits for signal processing and communication applications and image and video processing.Shahram Shirani received his B.S. in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran, and M.Sc. in Biomedical Engineering from Amirkabir University of Technology, Tehran, Iran, and Ph.D. in Electrical Engineering from University of British Columbia, Vancouver, Canada, in 1989, 1994 and 2000 respectively. Since 2000 he has been with the department of Electrical and Computer Engineering, McMaster University, where he is an assistant professor. His research interests include image and video compression, multimedia communications, and ultrasonic imaging. He is a member of technical committee of IEEE International Conference on Image Processing (ICIP). He is a licensed professional engineer and a member of Institute of Electrical and Electronics Engineers (IEEE).