超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

Low-field bulk defect generation during uniform carrier injection into the gate insulator of insulated gate field effect transistors at various temperatures

Low-field electron injection of up to 10¹⁹ e/cm² across the Si-SiO₂ interface into the gate insulator of an n-channel insulated gate field effect transistor using an optically assisted hot electron injection technique was conducted from room temperature down to 100K. It was found that the room temperature data could be modeled quite accurately by attributing all of the observed ΔV_t to generation of negatively charged defects whose generation follows a power law. At reduced temperatures, “structure” in the observed data indicated the presence of one shallow first order trap. In this case, a combination of a power law generation term and a single first order trap cross section was used, and is needed, to accurately model the data. It was also found that trap generation is enhanced significantly as the temperature is reduced. Threshold voltage shifts were shown by charge pumping measurements not to be associated with interface state generation under the low-field conditions employed. The results presented here indicate that even at very low applied oxide fields (1 MV/cm) hot electron injection not only results in the filling of existing traps, but also in the generation of new charged bulk defects whose generation rate increases as the temperature is reduced, or the injection current density is increased. These results also raise questions about some of the reports of small cross section trapping centers, ≤10⁻¹⁷ cm², since these were typically characterized by applying a only first order trapping model to high field and/or high current density injection data. Such aggressive injection conditions could very easily have resulted in the generation of charged bulk defects which could then be erroneously identified as one or more small cross section traps.     

Two types of neutral electron traps generated in the gate silicon dioxide

Electron trap generation in the gate oxide is a severe problem for the reliability of MOS devices, since it can cause stress-induced leakage current (SILC) and eventually lead to oxide breakdown. Although much effort has recently been made to understand the mechanism for the trap generation, the properties of the generated traps have received relatively less attention. The objective of this paper is to present unambiguous results, showing that two different types of neutral electron traps can be created by the same stress and to compare the properties of these two types of traps. Differences have been found in terms of their generation kinetics, trap filling, detrapping, and refilling after detrapping. The results also indicate that the energy levels of these two types of traps are different.     

Variation-resilient quantifiable plasma process induced damage monitoring

Many wafer manufacturing processes use plasma or other charge-based effects. The resulting currents can damage or destroy MOS gate oxides of transistors in products. This plasma induced damage (PID) can be in form of a reduction of the required lifetime of the devices, which can result in systematic early product failures in the field. PID damage and the resulting reliability reduction can be invisible in zero hour parameter and product tests, which can make it particularly dangerous.Products have to be made robust against PID by antenna design rules determined during technology development and verified in qualification measurements. To prevent early product fails due to unnoticed process excursions, fast wafer level reliability (fWLR) monitoring on the fully processed product wafer is required. The performance of PID fWLR on suitable test structures and the application of the fast diagnostic stresses will be presented. Details on options for data analysis for fast, sensitive and precise process excursion detection will be discussed based on a set of productive fWLR data following this methodology where false alarms are prevented.For some excursions detected by the fast diagnostic stresses the effect on the device lifetimes will be analysed with long term MOS device stresses. The physical reason for this will be discussed in a simple model of the devices' band structures.     

Wafer level reliability: Process control for reliability

Wafer Level Reliability test techniques can be used to provide fast feedback process control information regarding the reliability of the product of a semiconductor process. The purpose of wafer level reliability (WLR) tests is the measurement of variation in the materials comprising the semiconductor device. They are not intended as modeling tools for the quantification of the effect of stress on these materials. As such, WLR tests must provide a repeatable stress, independent of normal process variation. The results of these tests will be a measurement of the “rate of degradation” of the basic circuit elements caused by a standard stress.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown

Ultrathin gate and tunnel oxides in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and eventually causes dielectric breakdown. Oxide reliability, therefore, is a key concern in technology scaling for ultra-large scale integration (ULSI). Here we provide critical new insight into oxide degradation (and consequently, reliability) by a systematic study of five technologically relevant parameters, namely, stress-current density, oxide thickness, stress temperature, charge-injection polarity (gate versus substrate), and nitridation of pure oxide. For all five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps (distinct from the filling of intrinsic traps). Further, we observe that this correlation is independent of the trap polarity (positive versus negative). Based on this correlation, and based on the fundamental link between electronic properties and atomic structure, a physical-damage model of dielectric breakdown has been proposed. The concept of the physical-damage model is that the oxide suffers dielectric breakdown when physical damage due to broken bonds forms a defect-filled filamentary path in the oxide, that conducts excessive current. A good monitor of this physical damage is trap generation, which we believe is caused by physical bond breaking in the oxide and at the interface. The model has been quantified empirically by the correlation between trap generation and Q_bd     

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH₄) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.     

The effects of oxide traps on the MOS capacitance

The trapping of electrons and holes at a semiconductor surface by traps located in the oxide adjacent to the semiconductor has been considered. It is shown that the effective capture cross section of an oxide trap viewed by a carrier at the semiconductor surface is reduced by a factor which increases exponentially with the distance the trap is located from the interface. A pseudo-Fermi function in this position variable is developed which gives the probability that a trap will be filled (or emptied) in a measurement time, Tm. The trapping kinetics developed in the first part of the paper are applied to yield the full frequency and bias dependence of an MOS capacitor for an arbitrary spatial and energy trap distribution. Specific examples are given and the problem of voltage hysteresis is dealt with quantitatively. The conclusion is that very little information about the energy distribution and capture cross sections of the oxide traps is obtained from the analysis of MOS-capacitance curves.     

TDDB击穿特性评估薄介质层质量

与时间相关电介质击穿(TDDB)测量是评估厚度小于20nm薄栅介质层质量的重要方法.氧化层击穿前,隧穿电子和空穴在氧化层中或界面附近产生陷阱、界面态,当陷阱密度超过临界平均值 _bd时,发生击穿.击穿电量Q_bd值表征了介质层的质量.Q_bd值及其失效统计分布与测试电流密度、电场强度、温度及氧化层面积等有定量关系.TDDB的早期失效分布可以反映工艺引入的缺陷.TDDB可以直接评估氧化、氮化、清洗、刻蚀等工艺对厚度小于10nm的栅介质质量的影响.它是硅片级评估可靠性和预测EEPROM擦写次数的重要方法.     

Modeling of the transient response of substrate traps to thesubstrate voltage in GaAs FETs

The transient response of hole traps, related to the substrate in GaAs FETs, following an electric pulse applied to the substrate (or back gate) is accurately modeled. The modeled transient is found to be nonexponential. Excellent agreement between the experimental data and the model is obtained. The trap filling time required for the substrate hole traps is very sensitive to the difference between the Fermi energy and the trap energy     

A characterization model for ramp-voltage-stressed I-V characteristics of thin thermal oxides grown on silicon substrate

A theoretical model considering the effects of Fowler-Nordheim tunneling, image-force lowering, first-order trapping kinetics and impact ionization has been developed to characterize the ramp-voltage stressed current-voltage characteristics of thin oxides grown on silicon substrate. Based on the developed model, physical parameters of thin oxides such as effective total trapping density, trap capture cross section, recombination capture cross section and dielectric breakdown field can be extracted from the measurements. In general, the dielectric field strength of the oxide can be enhanced by increasing the amount of traps, which is especially important when the effective total trapping density is above 10¹³ cm⁻². Besides, smaller leakage current across thin oxide can be obtained with larger effective total trapping density and trap capture cross section. The recombination capture cross section is found to be in the order of 10⁻¹⁵–10⁻¹⁴ cm² for thin SiO₂ ranging from 92 to 196 Å. The dielectric field strength is enhanced and the leakage current is reduced as the trapped electron centroid shifts toward the cathode electrode, however, this is less prominent when the effective total trapping density is ⩽10¹² cm⁻².     

Oxide reliability: influence of interface roughness, structure layout, and depletion layer formation

The charge to breakdown Q_bd and the breakdown voltage V_bd distributions obtained on 7.5 and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms are discussed in terms of the GOX interface roughness and the depletion effects during the stress. The observed influence of the interface roughness on the GOX properties seems to be very sensitive to the gate polarity during the stress or the injection direction of electrons. Especially the roughness of the interface through which electrons are injected into the gate oxide influences the oxide reliability. The effect of the interface roughness turned out to depend strongly on the test acceleration level. A possibility of masking of the roughness (reduction of the “effective roughness”) of the GOX/Si interface as a result of strong depletion at higher accelerations is discussed.     

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value of average leakage current (I_avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I–V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.     

A new technique for determining the capture cross section of theoxide traps in MOS structures

The use of an oxide voltage relaxation spectroscopy technique based on voltage-electron fluence measurements on a MOS structure under high constant current stresses for determining the trapping parameters in thin oxide is discussed. Oxide voltage relaxation spectroscopy is essentially an ultralow-speed real-fluence differential sampling technique. This technique has the benefits of accuracy, speed, and convenience, and it is useful for the study of complex oxide trap phenomena. This method has been used to determine the capture cross section of the oxide traps in thin SiO₂     

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements

High field electrical stress effects on the mid-gap interface trap density (D_it0) and geometric mean capture cross sections (σ₀) in n-MOSFETs have been studied using the pulsed interface probing method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross section values caused by the Fowler–Nordheim (F–N) electrical stress. The decrease of mid-gap trap cross sections following the F–N tunneling injection is found. Our works also provide further insight into the influence of electrical stress on mid-gap interface trap generation in n-MOSFETs without the assumption of the constant capture cross section value during F–N stresses.     

Theory and experiments on surface 1/f noise

A theoretical low-frequency noise model for the epitaxial-channel surface field-effect structure is presented where random modulation of the channel conductance arises from fluctuation of charges trapped at the oxide trap states near the Si-SiO2interface. In this model, charge fluctuation in the oxide traps arises from carrier tunneling between the fast interface surface states and the oxide trap states. A second fluctuation, at higher frequencies, arises from the random thermal emission and capture of electrons and holes at the fast interface states through the thermal or Shockley-Read-Hall process. Different oxide trap densities were introduced into the interface region of the metal-oxide-silicon field-effect structures using a carefully controlled and reproducible oxygen heat treatment technique. Energy distributions of the oxide trap densities are obtained from capacitance measurements. Humps are observed between the flat band and the onset of strong surface inversion (lower half of the bandgap) in both the noise power and the oxide trap density versus gate voltage (or surface band bending) plots. Theoretical noise power calculations using the experimental oxide trap density profile from the capacitance-voltage data agree very well with the experimental noise humps in both magnitudes and fine structures. It is shown that the frequency spectra of noise depend strongly on the oxide trap density profile in the oxide. It is suggested that the oxide traps are due to the excess oxygen at the SiO2-Si interface.     

Anodic oxidation of Si in oxygen/chlorine plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO2interface was reduced from 7×10¹¹/cm².eV to 5×10¹¹/cm².eV at the midgap of Si; after annealing at 800°C in argon for 60 min, it was reduced to 8 × 10¹⁰/cm².eV, and did not return to the original value after heating the specimen to 800°C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasmaanodic SiO2films was reduced by annealing them at 800°C in argon, but SiO2films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

Plasma process induced damage detection by fast wafer level reliability monitoring for automotive applications

Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed.     

On a universal parameter of intrinsic oxide breakdown based onanalysis of trap-generation characteristics

It is found, even at room temperature, that hole fluence to breakdown Q_p of wet oxides is not a constant value for different oxide fields, but has a strong stress-electric-field dependence. Based on the neutral trap-generation characteristics related to SILC, this oxide-breakdown behavior dependent on the stress-electric field is analyzed. A novel model is proposed in which oxide breakdown is triggered when the current level of steady-state SILC via electron tunneling between traps reaches a critical value. From the spatial distribution of traps, we have concentrated on the critical trap pair whose electron-tunneling probability has the smallest value in the middle of the SiO₂ films. To verify this model, the convoluted trap density which is related to the electron-tunneling probability between the critical trap pair is investigated. As a result, it is found that this convoluted trap density remains constant regardless of stress-electric field and oxide thickness. This means that this convoluted trap density is a universal parameter for oxide breakdown