SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

RF inductors and capacitors integrated on silicon chip by CMOS compatible Cu interconnect technology

High-Q inductors and high-density capacitors have been designed and fabricated with a post-process of additional metal layers on the top of interconnect layers. The fabrication was carried out with advanced Cu interconnect technology, which was compatible with nowadays CMOS backend of line. The Q_max of inductors with inductance from 0.4 to 11 nH was over 11 on low-resistivity silicon substrates. Two kinds of structures of on-chip capacitors, MIM and MIMIM, have been studied. A capacitance of 1.75 fF/μm² has been achieved with MIMIM structure using Si₃N₄ as dielectric.     

Fabrication, characterisation and modelling of integrated on-silicon inductors

In this paper we present the design, fabrication and characterisation of passive inductors on a silicon substrate. These inductors were fabricated using a 10 μm minimum-feature CMOS process, with two aluminium layers and SiO₂ as the inter-level dielectric. Polygonal and circular inductors of four-and-a-half and seven-and-a-half turns were designed, fabricated and measured using a vector network analyser in the 40 MHz to 5 GHz range. Experimental results were compared to the predicted response of a simple equivalent electrical model. Compared to other reported inductors on silicon, the ones presented here show very good characteristics.     

Silicon oxynitride integrated waveguide for on-chip optical interconnects applications

This work explores the microfabrication technology for realizing miniature waveguide structure for on-chip optical interconnects applications. Thick oxynitride films were prepared by plasma enhanced chemical vapor deposition (PECVD) with N₂O, NH₃ and SiH₄ precursors. The composition and the bonding structure of the oxynitride films were investigated with Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy (XPS), and secondary ion mass spectroscopy. Results showed that the silicon oxynitride deposited with gas flow rates of NH₃/N₂O/SiH₄ = 10/400/10 (sccm) has favorable properties for integrated waveguide applications. The refractive index of this layer is about 1.5 and the layer has comparative low densities of O–H and N–H bonds. The hydrogen bonds can be further eliminated with high temperature annealing of the as-deposited film in nitrogen ambient and the propagation loss can be reduced significantly with thermal annealing. An integrated miniature waveguide with cross-section of 2 μm × 3 μm was realized with the proposed technology. The waveguide is able to transmit signal in either TE or TM mode with propagation loss <0.6 dB/cm (at 1550 nm) and bending radius of about 6 μm.     

Numerical and experimental analysis of the Sn3.5Ag0.75Cu solder joint reliability under thermal cycling

The Sn3.5Ag0.75Cu (SAC) solder joint reliability under thermal cycling was investigated by experiment and finite element method (FEM) analysis. SAC solder balls were reflowed on three Au metallization thicknesses, which are 0.1, 0.9, and 4.0 μm, respectively, by laser soldering. Little Cu–Ni–Au–Sn intermetallic compound (IMC) was formed at the interface of solder joints with 0.1 μm Au metallization even after 1000 thermal cycles. The morphology of AuSn₄ IMC with a small amount of Ni and Cu changed gradually from needle- to chunky-type for the solder joints with 0.9 μm Au metallization during thermal cycling. For solder joints with 4 μm Au metallization, the interfacial morphology between AuSn₄ and solder bulk became smoother, and AuSn₄ grew at the expense of AuSn and AuSn₂. The cracks mainly occurred through solder near the interface of solder/IMC on the component side for solder joints with 0.1 μm Au metallization after thermal shock, and the failure was characterized by intergranular cracking. The cracks of solder joints with 0.9 μm Au metallization were also observed at the same location, but the crack was not so significant. Only micro-cracks were found on the AuSn₄ IMC surface for solder joints with 4.0 μm Au metallization. The responses of stress and strain were investigated with nonlinear FEM, and the results correlated well with the experimental results.     

Breakdown spots of ultra-thin (EOT < 1.5 nm) HfO2/SiO2 stacks observed with enhanced—CAFM

In this work, the (gate) current versus (gate) voltage (I–V) characteristics and the dielectric breakdown (BD) of an ultra-thin HfO₂/SiO₂ stack is studied by enhanced conductive atomic force microscopy (ECAFM). The ECAFM is a CAFM with extended electrical performance. Using this new set up, different conduction modes have been observed before BD. The study of the BD spots has revealed that, as for SiO₂, the BD of the stack leads to modifications in the topography images and high conductive spots in the current images. The height of the hillocks observed in the topography images has been considered an indicator of structural damage.     

Process improvement of 0.13 μm Cu/Low K (Black Diamond) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.     

Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics

Effects of the base layer in Si₃N₄/SiON stack gate dielectrics, in particular, the physical thickness of the base layer, on the dielectric reliability, MOSFET performance and process controllability are investigated. It is found that the electrical characteristics such as TDDB lifetime as well as the Si₃N₄ film property in Si₃N₄/SiON stack dielectrics with the same capacitance oxide equivalent thickness strongly depend on the SiON-base layer thickness. From the TDDB measurements for both stress polarities and from the Si₃N₄ stoichiometry by the X-ray photoelectron spectroscopy analysis, the optimum SiON-base layer thickness is determined to be approximately 1 nm, in order to obtain longer TDDB lifetime and surperior n-ch MOSFET performance. The obtained results are considered to attribute to the nitrogen profile in the Si₃N₄/SiON stack dielectrics and the strained layer thickness near SiON/Si interface.     

The formation and growth of intermetallic compounds and shear strength at Sn–Zn solder/Au–Ni–Cu interfaces

The microstructures and shear strength of the interface between Sn–Zn lead-free solders and Au/Ni/Cu interface under thermal aging conditions was investigated. The intermetallic compounds (IMCs) at the interface between Sn–Zn solders and Au/Ni/Cu interface were analyzed by field emission scanning electron microscopy and transmission electron microscopy. The results showed the decrease in the shear strength of the interface with aging time and temperature. The solder ball with highly activated flux had about 8.2% increased shear strength than that with BGA/CSP flux. Imperfect wetting and many voids were observed in the fracture surface of the latter flux. The decreased shear strength was influenced by IMC growth and Zn grain coarsening. In the solder layer, Zn reacted with Au and then was transformed to the β-AuZn compound. Although AuZn grew first, three diffusion layers of γ-Ni₅Zn₂₁ compounds were formed after aging for 600 h at 150 °C. The layers divided by Ni₅Zn₂₁ (1), (2), and (3) were formed with the thickness of 0.7 μm, 4 μm, and 2 μm, respectively.     

Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs

An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm²) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm²/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Tin whisker formation of lead-free plated leadframes

This paper presents the evaluation results of whiskers on two kinds of lead-free finish materials at the plating temperature and under the reliability test. The rising plating temperature caused increasing the size of plating grain and shorting the growth of whisker. The whisker was grown under the temperature cycling the bent shaped in matte pure Sn finish and hillock shape in matte Sn–Bi. The whisker growth in Sn–Bi finish was shorter than that in Sn finish. In FeNi42 leadframe, the 8.0–10.0 μm diameter and the 25.0–45.0 μm long whisker was grown under 300 cycles. In the 300 cycles of Cu leadframe, only the nodule-shaped grew on the surface, and in the 600 cycles, a 3.0–4.0 μm short whisker grew. After 600 cycles, the 0.25 μm thin Ni₃Sn₄ formed on the Sn-plated FeNi42. However, we observed the amount of 0.76–1.14 μm thick Cu₆Sn₅ and 0.27 μm thin Cu₃Sn intermetallics were observed between the Sn and Cu interfaces. Therefore, the main growth factor of a whisker is the intermetallic compound in the Cu leadframe, and the coefficient of thermal expansion mismatch in FeNi42.     

Investigation of relation between intermetallic and tin whisker growths under ambient condition

The relation between the whisker growth and intermetallic on various lead-free finish materials that have been stored at ambient condition for 2 yrs (6.3 × 10⁷ s) is investigated. The matte Sn plated leadframe (LF) had the needle-shaped whisker and the nodule-shaped whisker was observed on the semi-bright Sn plated LF. Both the Sn plated LFs had a same columnar grain structure and both whiskers were grown in connection with the scalloped intermetallic compound (IMC) layer. The morphology of the IMC layer is similar, regardless of the area which has whisker or not. On the Sn–Bi finish and bright Sn plated LF, hillock-shaped and sparsely grown branch-shaped whiskers were observed, respectively. The IMC grew irregularly under both the areas with or without whisker. The IMC growth along the Sn grain boundaries generated inner compressive stress at the plating layer. Atomic force microscopy (AFM) profiling analysis is useful for characterization the IMC growth on the Sn and Cu interface. The measured root mean square (RMS) values IMC roughness on semi-bright Sn, matte Sn, and bright Sn plated LF were 1.82 μm, 1.46 μm, and 0.63 μm, respectively. However, there is no direct relation between whisker growth and the RMS value. Two layers of η′-Cu₆Sn₅ were observed using field emission transmission electron microscopy (FE-TEM): fine grains and coarse grains existed over the fine grains.     

An unusual mechanical failure mode in gold ballbonds at 50 μm pitch due to degradation at the Au–Au4Al interface during ageing in air at 175 °C

While investigating the bake test reliability of gold ball bonds in air at 175 °C an unusual failure mode was encountered that can strictly be classified as a ball lift but which has pull strengths as high as normal neck breaks. The failure mode is termed a high strength ball lift (HSBL) and is distinguished by partial de-bonding between the gold ball and intermetallic compound. The partial de-bonding occurs as a ring or annulus that starts from the outside of the ball and grows inwards toward the ball centre, occurring within the Au₄Al compound layer and between the Au₄Al and Au ball while the remaining part of the gold ball is well-bonded to the Au₄Al at the centre of the bondpad. During pull testing, the de-bonded outer ring acts as a notch that propagates a blunt crack into the gold ball resulting in high pull strengths. As ageing time increases the de-bonded region grows larger and advances inwards towards the ball centre. EDX of both types of ball-lifts indicates higher levels of oxygen on the Au₄Al surface that suggests annulus growth may be partially due to oxidation of the intermetallic. The number of HSBL failures and the point in time at which they occur is observed to depend on the bonded ball squash height, a relatively easily controlled parameter in gold ballbonding. When devices with targeted squash heights (TSH) of 6 μm, 7 μm and 8 μm are isothermally aged, zero ball lifts are only obtained at 7 μm squash height. HSBL failures are encountered earlier at the 6 μm TSH than at 8 μm TSH and as the de-bonded region progresses further inwards during baking, the HSBL’s are observed to transition to low strength ball lifts (LSBL) as the load-bearing area of the ball is reduced. The dependence of failure mode on squash height is believed to be related to interactions between bonded ball stress, intrinsic intermetallic growth stresses and thermo-chemical degradation of the Au₄Al intermetallic compound.     

Microstructure and electromigration in copper damascene lines

Grain sizes and crystallographic orientations of Cu were analyzed versus linewidth in damascene Cu interconnects. Pure bamboo lines were not obtained because grain size decreased as linewidth was reduced. Comparison of electromigration results, for wide line Chemical vapor deposition-Cu (3 μm) polycrystalline structure, and narrow lines (0.5 μm) quasi-bamboo structure, provided almost the same activation energy E_a0.65 eV, even though the poor (2 0 0) texture has rotated in the film plane for the narrow damascene lines. These results are in agreement with copper diffusion involving surface diffusion. Besides, even with a polycrystalline crystallographic orientation, PVD-Cu samples showed a better activation energy value E_a=1.02 eV.     

Effective work function of NiSi/HfO2 gate stacks measured with X-ray photoelectron spectroscopy

A method to measure an effective work function, WF_eff, of a metal electrode in contact with particular dielectric in a metal–oxide–semiconductor stack is proposed by in situ monitoring core level binding energy shifts of dielectric constituents upon deposition of an ultrathin metallic layer on top. The proposed method is utilized to measure relative changes in WF_eff between Ni and NiSi electrodes in contact with HfO₂, as well as to investigate the role of Sb and Ti δ-layers at NiSi/HfO₂ interface.     

Atomic Layer Deposition in the Production of a Gate HkMG Stack Structure with a Minimum Topological Size of 32 nm

The plasma-enhanced atomic layer deposition (PEALD) of a High-K Dielectric and Metal Gate (HkMG) stack for MIS transistors, including the subgate HfO₂ (2–4 nm) dielectric layer, the ultrathin metallic stabilizing hafnium nitride HfN (1–3 nm) layer, and the basic metallic gate layer from tantalum nitride ТаN (10–20 nm), on silicon plates with a diameter of 200 mm is studied. The spectral ellipsometry method is applied to measure the homogeneity of the deposited film thickness. The dielectric constant of the dielectric in the stack, the leak current, and the breakdown voltage are examined. The four-probe method is used to study the specific electric resistance of tantalum nitride deposited by the atomic layer deposition ALD method. The film thickness homogeneity as a function of the ALD process parameters is examined. The specific resistance of the metallic TaN layer as a function of the composition and parameters of the plasma discharge are studied.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.     

Percolative approach for failure time prediction of thin film interconnects under high current stress

The present study deals with the use of a rapid and non-destructive technique based on percolation theory to predict failure times during the reliability analysis of thin film interconnects under high current stress. Al–Cu test structures were used for this purpose. Small populations of these structures of similar geometry were subjected to extremely high current density conditions (30.6 and 46.6 MA/cm²) and their corresponding failure times were noted. The critical exponent (μ_B) for the Al–Cu structures stressed at both the current densities was calculated to be 0.16. The value of the μ_B showed that the structures undergo biased percolation and have similar failure mechanisms (due to Joule heating) at both current densities. The calculated value of μ_B was used to predict the failure times of the fuses under each of the current stresses. The discrepancy between the experimental failure time and the predicted failure time was significantly low (<12%) in both cases thus expressing the strength of this prediction technique.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.