Optimal operation of coreless PCB transformer-isolated gate drivecircuits with wide switching frequency range

Gate drive circuits for power MOSFETs and insulated gate bipolar transistors (IGBTs) often require electrical isolation. Coreless printed circuit board (PCB) transformers have been shown to have desirable characteristics from a few hundreds of hertz to a few megahertz and can be used for both power and signal transfer at low-power level. At low operating frequency, the magnetizing inductance has such low impedance that the driving power requirement could become excessive. This paper describes the use of a coreless PCB transformer for isolated gate drive circuits over a wide-frequency range. Based on a resonance concept, the optimal operating condition that minimizes the power consumption of the gate drive circuits is developed and verified with experiments. The coreless PCB transformer demonstrated here confirms a fundamental concept that the size and volume of a magnetic core could approach zero and become zero if the operating frequency is sufficiently high. Coreless PCB transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits and low-power converters. Their sizes can be much smaller than those of typical core-based pulse transformers. The electrical isolation of a PCB is much higher than that of an optocoupler     

High-Voltage Auxiliary Power Supply Using Series-Connected MOSFETs and Floating Self-Driving Technique

This paper deals with high-voltage auxiliary switching-mode power supplies (SMPSs). An overview of the state of the art is given, and a novel solution is proposed. The proposed solution is based on a single-ended flyback or forward topology with the main switch arranged as a series connection of two metal-oxide-semiconductor field-effect transistors (MOSFETs). The bottom MOSFET is driven directly by an ordinary control circuit and gate driver, while the top MOSFET is driven by a floating self-supplied gate driver. The floating gate driver is connected to the input filter capacitors' midpoint. This gate driver plays two roles: driving of the top MOSFET and control of distribution of the blocking voltage among the series-connected MOSFETs, in steady state as well as during commutation. The series connection of lower voltage MOSFETs has two important advantages compared to that of a single high-voltage MOSFET: lower conduction losses and lower cost. When several switches are series connected, each switch supports a fraction of the total blocking voltage, and therefore, each switch can be rated for lower voltage. The total on-state resistance and the cost of such a switch arrangement are lower compared to that of a single switch that supports the full blocking voltage. The proposed SMPS is theoretically analyzed and experimentally verified. The experimental results are presented and discussed.     

Gate Driver Supplies and Dead Time Management Circuits for AC to AC Converters

This paper presents an original implementation of a technique in ac-to-ac power converters to power the gate drivers of power transistors. AC to ac converters are well known for the complexity of their implementation due to the large number of power transistors required, many of which have different potential references. This requires a consequent number of insulated gate drivers and corresponding power supplies. Besides, MOS–MOS switching transitions (characterized by switching transitions among transistors without the introduction of freewheeling diode conduction time), typical of these converters, are complex to manage and often lead to voltage or current overshoots. The gate driver powering technique presented in this paper simplifies the global implementation of the converter as well as the management of MOS–MOS switching transitions. The proposed technique harvests energy from the power side, when this energy is available, in order to redistribute this energy to the transistor drivers. This original self-powering technique significantly simplifies the implementation of the transistor since it can be integrated within the power switch to be controlled. The immediate benefit is a reduced number of elements to be implemented, thus providing a cost-effective solution. As an additional benefit, the proposed technique simplifies the management of high-stress switching transitions. Indeed, the gate driver power supplies are designed to be sensitive to positive d$v$/d$t$, a feature that allows self-powering during the dead time of switching transitions. This leads to a reduction in both dead time duration and voltage overshoots, as validated by a practical implementation.      

Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

Power switch transistors are very effective in cutting the leakage currents of digital circuits in a deep-freeze mode, by de-supplying unused blocks. Among existing power switch transistors, Super Cut-off CMOS (SCCMOS) is the most suited to a low supply voltage environment since it uses a low threshold voltage transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. A polarization circuit, that automatically finds the optimal bias voltage whatever the environment conditions, was therefore designed and fabricated. This circuit, made in Bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature. A very simple scheme is also presented to alleviate the voltage stress applied on the dielectric in case of an ageing of the latter, increasing its time-to-breakdown by several orders of magnitude.     

Autonomous control technique for high-performance switches

A method for creating high-performance switch modules from power transistors and simple control circuits is presented. The method is based on switching function principles by which any type of switch can be represented by an ideal switch in combination with basic logic elements. These high-performance modules can be configured to emulate diodes, thyristors, special resonant devices, or nearly any other switch type. The control is autonomous-it depends on the terminal behavior and external gate signals and requires no additional information from the application circuit. Experimental examples of several switch modules in low-voltage power converters are given. The experimental modules use power MOSFETs and give performance similar to that of synchronous rectifiers but with much greater flexibility. An example is noted in which a module configured to emulate a silicon controlled rectifier (SCR) shows voltage drops below 0.25 V at several amperes of forward current     

Improving FET Switch Linearity

RF field-effect transistors, especially pseudomorphic high-electron mobility transistors (pHEMTs), are commonly used as switches in communication applications. These small high-speed devices are vital for routing and conveying signals in such uses. The important characteristics of pHEMTs, besides their small size, are their high-frequency capability, insertion loss, isolation, power handling, switching speed, and linearity. A topology using a pair of simple but modified series and shunt elements was designed to improve upon the linearity of an RF switch. Each element of the switch was composed of a single, unbiased, but relatively long pHEMT, which was designed for the test. By shifting the position of the gate asymmetrically toward the source terminal in these transistors, it was found that the linearity was improved without cost to other performance parameters     

Snubberless voltage sharing of series-connected insulated-gatedevices by a novel gate control strategy

Insulated gate devices, such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), are increasingly used in high-voltage power converters where a request for fast power switches is growing. Series connection of devices is a viable approach to manage voltages higher than the blocking voltage of the single device. The main problem in such an application is to guarantee the voltage balance across the devices both in steady-state and during switching transients. In this paper, a novel approach is presented, which is used to equalize the voltage sharing during the switching transients. The main advantages of the proposed method consist in avoiding the traditional use of the snubber capacitors, in the output power side, and in working on the gate side. The application of the proposed gate drive technique is firstly discussed and compared with different solutions, hence, validated by experimental tests applied to the control of series connected devices. Finally, a comparison is performed between the transient behaviors of two different configurations: a single switch with high-voltage blocking capability, and in alternative a series of two devices which together ensure the voltage blocking capability of the single switch. The better performances of the latter configuration, working with the proposed control circuit, over the former have been experimentally demonstrated     

Performance optimizing on multi-function MMIC design

Integration of GaAs BiFET (bipolar-FET) devices to obtain the optimum performance for multiple functions of MMIC design has been achieved. In this study, heterojunction bipolar transistors (HBTs), enhancement mode pseudomorphic HEMTs (E-pHEMTs), and depletion mode pHEMTs are developed for potential applications, including the integration of HBT power amplifier circuitry with pHEMT-based bias control, logic, RF switch, and low-noise amplifier circuitries. Critical processes including gate photolithography and gate recess control are presented and discussed in detail. The enhancement-depletion modes of pHEMT, HBT electrical performance, and uniformity are investigated comprehensively. In addition, power amplifiers and high power switches based on BiFET technology are investigated.     

Estimation and Measurement of Junction Temperatures in a Three-Level Voltage Source Converter

The design of a power converter must guarantee that the operating junction temperatures thetav_j of all devices do not exceed their limits under all specified operating conditions. Usually, this is ensured by a simulative or analytical junction temperature estimation based on simple electrical and thermal models and semiconductor datasheet values. This paper discusses the difficulties and quantifies the limitations of this approach on the example of a three-level neutral point clamped voltage source converter (NPC VSC) with insulated gate bipolar transistors. The calculations are compared to the results of direct junction temperature measurements with an infrared camera. The paper also provides the experimental proof for the unequal loss and junction temperature distribution in the three-level NPC VSC     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Actively clamped zero-current-switching quasi-resonant convertersusing IGBTs

Conventional zero-current-switching quasi-resonant power converters (ZCS-QRCs) suffer from the disadvantages of high switch current stress and variable switching frequency. This paper proposes the use of a “current-clamping circuit” to overcome these disadvantages. By incorporating such a circuit into the family of ZCS-QRCs, a new family of actively clamped ZCS-QRCs using insulated gate bipolar transistors (IGBTs) is derived. These power converters feature high (and constant) switching frequency and zero-current turn-off (without increased current stress), which are particularly useful for high-power applications where minority-carrier semiconductor devices (such as IGBTs and bipolar junction transistors) are used as power switches. The design criteria, simulation and experimental results are reported     

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

As the characteristics of insulated gate transistors [like metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of di/dt at turn-on and dv/dt at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.     

基于有机薄膜晶体管电特性曲线获取迁移率方法的研究

场效应迁移率是描述有机薄膜晶体管(OTFT)性能的 重要参数之一,目前OTFT场效应迁移率主要根据实验测得OTFT电特性曲线通过拟合计算方法 获得。本文针对这种方法进行深入研究发现,OTFT的场效应迁 移率与其工作状态有关。在线性工作状态下,OTFT的线性区场效应迁移率随 着 栅电压的增加而增大;在饱和工作状态下,当漏电压VD>1.5VGmax时,饱和区场效应迁移率 为一定值,表明采用此值表征OTFT的电性能更加客观和精确。     

Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications.      

Development of a Scalable Power Semiconductor Switch (SPSS)

This paper presents the design and development of a 4800-V, 300-A, 10-kHz scalable power semiconductor switch (SPSS) based on series connecting low voltage insulated gate bipolar transistors (IGBTs). The static and dynamic voltage balance among IGBTs is achieved using a hybrid approach of active clamp circuit and an active gate control that is also effective during tail current phase. The developed SPSS derives its control power directly from the main power bus. Control, packaging, and thermal characteristics are an integral part of the SPSS design. From a user's standpoint, the SPSS is a three-terminal optically controlled high-power switch. Experimental evaluation of the prototype SPSS shows it fully achieved the design objectives. In principle, the approach can be extended to building switches with higher voltages, currents, and switching frequencies, or even with other types of devices than IGBTs     

一种高侧功率开关的输出短路保护电路

提出了一种智能高侧功率开关的短路保护电路,包括输出短路检测电路、延时信号产生电路和栅源电压限制电路。采用NMOS管用作功率管,使电路短路时仍处于安全工作区内,提升了高侧功率开关的可靠性。采用0.6μm HV SOI工艺对该短路保护电路进行了仿真验证。仿真结果表明,在硬开关故障和负载短路两种情况下,功率管保持处于安全工作区内。     

Reducing IGBT losses in ZCS series resonant converters

The fundamental operational parameter that controls the losses in series resonant power converters was found to be the reflected DC voltage transfer ratio. Losses which are a function of the average current (such as conduction losses of insulated gate bipolar transistors and diodes) are independent of the switching frequency. Losses which are associated with the RMS current are a function of both the reflected DC voltage ratio and the switching frequency ratio. Universal and normalized graphs, derived in this paper, can be conveniently used to assess the expected RMS and average current conduction losses under any given operational conditions. The residual switching losses in zero-current-switching series resonant power converters operating in continuous current mode can be reduced by simple current snubbers placed in the commutation circuits. The experimental results of this paper confirm the theoretical predictions and demonstrate that the turn-on snubbers can reduce switching losses by about 1.5% at a switching frequency of 65 kHz     

An improved ZCS-PWM commutation cell for IGBT's application

An improved zero-current-switching pulsewidth-modulation (ZCS-PWM) commutation cell is proposed, which is suitable for high-power applications using insulated gate bipolar transistors (IGBTs) as the power switches. It provides ZCS operation for active switches with low-current stress without voltage stress and PWM operating at constant frequency. The main advantage of this cell is a substantial reduction of the resonant current peak through the main switch during the commutation process. Therefore, the RMS current through it is very close to that observed in the hard-switching PWM converters. Also, small ratings auxiliary components can be used. To demonstrate the feasibility of the proposed ZCS-PWM commutation cell, it was applied to a boost converter. Operating principles, theoretical analysis, design guidelines and a design example are described and verified by experimental results obtained from a prototype operating at 40 kHz, with an input voltage rated at 155 V and 1 kW output power. The measured efficiency of the improved ZCS-PWM boost converter is presented and compared with that of hard-switching boost converter and with some ZCS-PWM boost converters presented in the literature. Finally, this paper presents the application of the proposed soft-switching technique in DC-DC nonisolated power converters     

High-speed frequency dividers using GaAs/GaAlAs high-electron-mobility transistors

Very-high-speed divide-by-four circuits have been fabricated by using modulation-doped GaAs/GaAlAs high-electron-mobility transistors. The circuits consist of two T-connected D-flip-flops and are capable of operating at 3.6 GHz with a power dissipation of 0.46 mW per gate at room temperature, and at 5.2 GHz with a power dissipation of 0.78 mW per gate at 77 K. The speed-power products achieved are the lowest ever reported.