The performance of submicrometer gate length GaAs MESFET's

The influence of gate length, active layer thickness, and buffer layer current upon the steady-state and RF parameters of short gate length GaAs MESFET's is investigated using a two-dimensional model that accounts for electron energy relaxation effects. For devices of similar pinchoff voltage, the saturation currents are approximately the same, but the presence of substrate conduction in a device greatly reduces its transconductance and gain-bandwidth product. The effect upon frequency response due to gate length, donor profile, gate resistance, and source inductance is numerically evaluated. The model is shown to be in reasonable agreement with measured submicrometer device characteristics.     

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I/sub D/ etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs.     

Sub-100 nm CMOS circuit performance with high-K gate dielectrics

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO₂ is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance.     

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in f/sub T/, f/sub max/, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.     

The effect of fluorine in silicon dioxide gate dielectrics

The effect of post-oxide-growth fluorine incorporation in gate dielectrics is reported. Fluorine was introduced through ion implantation into polysilicon and diffused into the gate oxide, as indicated by SIMS measurements. No great decrease in the breakdown field was observed, although a decrease in charge-to-breakdown was seen. Interface characteristics also improved with medium to high doses of fluoride. High doses were found to grow additional oxide. NMOS FETs showed increased immunity to hot-electron-induced stress. These results are explained by a model wherein fluorine bonds to silicon, and the displaced oxygen grows the additional oxide     

Modeling of submicrometer gate GaAs field effect transistors

Before describing the mainFet modelings today available, the main technological evolutions ofMesfet andTegfet are summarized. It is brought some information on the various physical effects that occur in the devices and that must be taken into account in the models. It is shown that the different kinds of modelings (Monte Carlo, two dimensional, one dimensional) constitute a continuous chain, where the different elements appear strictly complementary. Finally, the present situation concerning modeling ofMesfet andTegfet will be presented.     

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

Capacitance-Voltage measurement method for ultrathin gate dielectrics using LC resonance circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.     

Identification of gate electrode discontinuities in submicron CMOStechnologies, and effect on circuit performance

An experiment to determine the effect of gate electrode resistivity on circuit speed gave unexpected results: circuits with the lowest sheet resistance had the poorest circuit speed. Explanation of this behaviour required development of a new high-frequency method of measuring the impedance of the gate electrode. This method revealed that the circuits with a composite gate electrode had been formed with a partial discontinuity. The measurement technique is described, and the evidence of the discontinuity is shown. The effect of the discontinuity on device and circuit speed is demonstrated     

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si/sub 3/N/sub 4//SiO/sub 2/, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement.     

Hot carrier effects on analog performance of N- and P-MOSFET's withoxynitride gate dielectrics

In this paper we report the impact of hot-carrier stress on analog performance of n- and p-MOSFET's with conventional oxide, NH₃-nitrided oxide (RTN) and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics. Changes due to hot-carrier stress in crucial analog parameters viz., drain output resistance, voltage gain, and input offset voltage of a source coupled differential MOSFET pair are investigated. Results show that RTN/RTO gate dielectrics suppress degradation of analog parameters in n-MOSFET's but increase it slightly in p-MOSFET's, as compared to conventional oxide MOSFET's     

Degradation of high-K LA2O3 gate dielectrics using progressive electrical stress

The evolution of the leakage current in high-K lanthanum oxide films in MOS devices caused by the application of progressive electrical stress is investigated. The degradation method consists in performing successive voltage sweeps using an ever increasing voltage range with the aim of generating incremental damage to the structure in a controlled manner. We show that the total current flowing through the device can be thought of as formed by two parallel components, one associated with the tunneling mechanism and the other one associated with diode-like conduction. This latter component evolves with applied stress. It is shown the importance of considering series and parallel resistances in order to account for the right shape of the conduction characteristics. Analytical expressions for both current contributions suitable for all stages of degradation and bias conditions are provided.     

Power-supply voltage impact on circuit performance for half andlower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E_cL_eff, where E_c is the critical electric field necessary to cause carrier velocity saturation and L_eff is the effective channel length, is introduced. Experimental results confirmed that 1.1E_cL_eff predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 μm). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E_cL_eff can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6-μm channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E_cL_eff     

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

Plasma process-induced damage continues to be a great threat and concern in the modern CMOS technologies. This article concentrates on NMOS vs. PMOS device sensitivity to plasma charging originating from the various processing steps. This dependence is studied with respect to the gate oxide thickness, and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. Specific studies are performed to explore the resistance to the charging damage in CMOS devices with a 50 Å gate oxide grown with various oxidation processes.