New low-stress PECVD poly-SiGe Layers for MEMS

Thick poly-SiGe layers, deposited by plasma-enhanced chemical vapor deposition (PECVD), are very promising structural layers for use in microaccelerometers, microgyroscopes or for thin-film encapsulation, especially for applications where the thermal budget is limited. In this work it is shown for the first time that these layers are an attractive alternative to low-pressure CVD (LPCVD) poly-Si or poly-SiGe because of their high growth rate (100-200 nm/min) and low deposition temperature (520/spl deg/C-590/spl deg/C). The combination of both of these features is impossible to achieve with either LPCVD SiGe (2-30 nm/min growth rate) or LPCVD poly-Si (annealing temperature higher than 900/spl deg/C to achieve structural layer having low tensile stress). Additional advantages are that no nucleation layer is needed (deposition directly on SiO/sub 2/ is possible) and that the as-deposited layers are polycrystalline. No stress or dopant activation anneal of the structural layer is needed since in situ phosphorus doping gives an as-deposited tensile stress down to 20 MPa, and a resistivity of 10 m/spl Omega/-cm to 30 m/spl Omega/-cm. With in situ boron doping, resistivities down to 0.6 m/spl Omega/-cm are possible. The use of these films as an encapsulation layer above an accelerometer is shown.     

Fabrication and measured performance of a first-generation microthermoelectric cooler

The measured performance of a column-type microthermoelectric cooler, fabricated using vapor-deposited thermoelectric films and patterned using photolithography processes, is reported. The columns, made of p-type Sb/sub 2/Te/sub 3/ and n-type Bi/sub 2/Te/sub 3/ with an average thickness of 4.5 /spl mu/m, are connected using Cr/Au/Ti/Pt layers at the hot junctions, and Cr/Au layers at the cold junctions. The measured Seebeck coefficient and electrical resistivity of the thermoelectric films, which were deposited with a substrate temperature of 130/spl deg/C, are -74 /spl mu/V/K and 3.6/spl times/10/sup -5/ /spl Omega/-m (n-type, power factor of 0.15 mW/K/sup 2/-m), and 97 /spl mu/V/K and 3.1/spl times/10/sup -5/ /spl Omega/-m (p-type, power factor of 0.30 mW/K/sup 2/-m). The cooling performance of devices with 60 thermoelectric pairs and a column width of 40 /spl mu/m is evaluated under a minimal cooling load (thermobuoyant surface convection and surface radiation). The average cooling achieved is about 1 K. Fabrication challenges include the reduction of the column width, implementation of higher substrate temperatures for optimum thermoelectric properties, and improvements of the top connector patterning and deposition.     

VHF single crystal silicon capacitive elliptic bulk-mode disk resonators-part II: implementation and characterization

This work, the second of two parts, reports on the implementation and characterization of high-quality factor (Q) side-supported single crystal silicon (SCS) disk resonators. The resonators are fabricated on SOI substrates using a HARPSS-based fabrication process and are 3 to 18 /spl mu/m thick. They consist of a single crystal silicon resonant disk structure and trench-refilled polysilicon drive and sense electrodes. The fabricated resonators have self-aligned, ultra-narrow capacitive gaps in the order of 100 nm. Quality factors of up to 46 000 in 100 mTorr vacuum and 26000 at atmospheric pressure are exhibited by 18 /spl mu/m thick SCS disk resonators of 30 /spl mu/m in diameter, operating in their elliptical bulk-mode at /spl sim/150 MHz. Motional resistance as low as 43.3 k/spl Omega/ was measured for an 18-/spl mu/m-thick resonator with 160 nm capacitive gaps at 149.3 MHz. The measured electrostatic frequency tuning of a 3-/spl mu/m-thick device with 120 nm capacitive gaps shows a tuning slope of -2.6 ppm/V. The temperature coefficient of frequency for this resonator is also measured to be -26 ppm//spl deg/C in the temperature range from 20 to 150/spl deg/C. The measurement results coincide with the electromechanical modeling presented in Part I.     

A low-temperature thin-film electroplated metal vacuum package

This paper presents a packaging technology that employs an electroplated nickel film to vacuum seal a MEMS structure at the wafer level. The package is fabricated in a low-temperature (<250/spl deg/C) 3-mask process by electroplating a 40-/spl mu/m-thick nickel film over an 8-/spl mu/m sacrificial photoresist that is removed prior to package sealing. A large fluidic access port enables an 800/spl times/800 /spl mu/m package to be released in less than three hours. MEMS device release is performed after the formation of the first level package. The maximum fabrication temperature of 250/spl deg/C represents the lowest temperature ever reported for thin film packages (previous low /spl sim/400/spl deg/C). Implementation of electrical feedthroughs in this process requires no planarization. Several mechanisms, based upon localized melting and Pb/Sn solder bumping, for sealing low fluidic resistance feedthroughs have been investigated. This package has been fabricated with an integrated Pirani gauge to further characterize the different sealing technologies. These gauges have been used to establish the hermeticity of the different sealing technologies and have measured a sealing pressure of /spl sim/1.5 torr. Short-term (/spl sim/several weeks) reliability data is also presented.     

Characterization of Polycrystalline Silicon-Germanium Film Deposition for Modularly Integrated MEMS Applications

The deposition of in situ boron-doped polycrystalline silicon-germanium (poly-SiGe) films in a conventional low-pressure chemical-vapor deposition reactor has been characterized using the design of experiments method. The dependencies of deposition rate, resistivity, average residual stress, strain gradient, and wet etch rate in hydrogen peroxide solution are presented. Structural layer requirements for general microelectromechanical system applications can be met within the process temperature constraint imposed by complementary metal-oxide-semiconductor (CMOS) electronics. However, residual stress and strain gradient requirements for inertial sensor applications will be difficult to meet with a single homogeneous layer of poly-SiGe that is about 2 mum thick. By correlating stress depth profile measurements with cross-sectional transmission electron microscopy images, we conclude that the large strain gradient is due to highly compressive stress in the lower (initially deposited) region of the film. For films deposited at very low temperature (near the range of amorphous film deposition), in situ boron doping enhances film crystallinity and reduces the strain gradient     

Analysis of piezoresistance in p-type silicon for mechanical sensors

Typical p-type silicon mechanical sensors are designed to operate under temperature range from /spl sim/173 K to /spl sim/373 K and subjected to stress less than /spl sim/100 MPa. The operation range is mainly restricted by the electrical and mechanical properties of silicon. The authors derived an approximate piezoresistance equation valid for typical operation range of the p-type silicon mechanical sensors, from valence band model of Bir and Pikus taking into account the spin-orbit interaction. The piezoresistance in p-type silicon was analyzed based on hole transfer and conduction mass shift due to stress. These mechanisms were introduced by Suzuki et al. [1984] to interpret piezoresistance in p-type silicon, based on the valence band equation in the vicinity of k=0. Under the typical operation range for p-type silicon mechanical sensors, holes are located where the value of k is relatively large, i.e., off k=0 and degenerate band split due to stress is incomplete. The hole behavior in the valence band was compatible with the typical operation range for p-type silicon mechanical sensors.     

A monolithic three-axis micro-g micromachined silicon capacitive accelerometer

A monolithic three-axis micro-g resolution silicon capacitive accelerometer system utilizing a combined surface and bulk micromachining technology is demonstrated. The accelerometer system consists of three individual single-axis accelerometers fabricated in a single substrate using a common fabrication process. All three devices have 475-/spl mu/m-thick silicon proof-mass, large area polysilicon sense/drive electrodes, and small sensing gap (<1.5 /spl mu/m) formed by a2004 sacrificial oxide layer. The fabricated accelerometer is 7/spl times/9 mm/sup 2/ in size, has 100 Hz bandwidth, >/spl sim/5 pF/g measured sensitivity and calculated sub-/spl mu/g//spl radic/Hz mechanical noise floor for all three axes. The total measured noise floor of the hybrid accelerometer assembled with a CMOS interface circuit is 1.60 /spl mu/g//spl radic/Hz (>1.5 kHz) and 1.08 /spl mu/g//spl radic/Hz (>600 Hz) for in-plane and out-of-plane devices, respectively.     

The critical role of environment in fatigue damage accumulation in deep-reactive ion-etched single-crystal silicon structural films

The importance of service environment to the fatigue resistance of n/sup +/-type, 10 /spl mu/m thick, deep-reactive ion-etched (DRIE) silicon structural films used in microelectromechanical systems (MEMS) was characterized by testing of electrostatically actuated resonators (natural frequency, f/sub 0/, /spl sim/40 kHz) in controlled atmospheres. Stress-life (S-N) fatigue tests conducted in 30/spl deg/C, 50% relative humidity (R.H.) air demonstrated the fatigue susceptibility of silicon films. Further characterization of the films in medium vacuum and 25% R.H. air at various stress amplitudes revealed that the rates of fatigue damage accumulation (measured via resonant frequency changes) are strongly sensitive to both stress amplitude and, more importantly, humidity. Scanning electron microscopy of high-cycle fatigue fracture surfaces (cycles to failure, N/sub f/>1/spl times/10/sup 9/) revealed clear failure origins that were not observed in short-life (N/sub f/<1/spl times/10/sup 4/) specimens. Reaction-layer and microcracking mechanisms for fatigue of silicon films are discussed in light of this empirical evidence for the critical role of service environment during damage accumulation under cyclic loading conditions.     

Polymer-based cantilevers with integrated electrodes

An innovative release method of polymer cantilevers with embedded integrated metal electrodes is presented. The fabrication is based on the lithographic patterning of the electrode layout on a wafer surface, covered by two layers of SU-8 polymer: a 10-/spl mu/m-thick photo-structured layer for the cantilever, and a 200-/spl mu/m-thick layer for the chip body. The releasing method is based on dry etching of a 2-/spl mu/m-thick sacrificial polysilicon layer. Devices with complex electrode layout embedded in free-standing 500-/spl mu/m-long and 100-/spl mu/m-wide SU-8 cantilever were fabricated and tested. We have optimized major fabrication steps such as the optimization of the SU-8 chip geometry for reduced residual stress and for enhanced underetching, and by defining multiple metal layers [titanium (Ti), aluminum (Al), bismuth (Bi)] for improved adhesion between metallic electrodes and polymer. The process was validated for a miniature 2/spl times/2 /spl mu/m/sup 2/ Hall-sensor integrated at the apex of a polymer microcantilever for scanning magnetic field sensing. The cantilever has a spring constant of /spl cong/1 N/m and a resonance frequency of /spl cong/17 kHz. Galvanometric characterization of the Hall sensor showed an input/output resistance of 200/spl Omega/, a device sensitivity of 0.05 V/AT and a minimum detectable magnetic flux density of 9 /spl mu/T/Hz/sup 1/2/ at frequencies above 1 kHz at room temperature. Quantitative magnetic field measurements of a microcoil were performed. The generic method allows for a stable integration of electrodes into polymers MEMS and it can readily be used for other types of microsensors where conducting metal electrodes are integrated in cantilevers for advanced scanning probe sensing applications.     

The fabrication of all-diamond packaging panels with built-in interconnects for wireless integrated microsystems

To explore polycrystalline diamond (poly-C) as a packaging material for wireless integrated microsystems (WIMS), a new fabrication technology has been developed to fabricate thick WIMS packaging panels with built-in interconnects. An ultrafast poly-C growth technique, used in this study, involves electrophoresis seeding and filling of dry-etched Si channels by undoped poly-C followed by removal of Si. A second layer of highly B-doped poly-C, which acts as a built-in interconnect, is deposited on the backside of undoped poly-C layer. The lowest resistivity values demonstrated on control samples are in the range from 0.003 to 0.31 /spl Omega/-cm. The results show that, by increasing the poly-C growth areas through the use of 2-/spl mu/m-wide Si channels, the poly-C growth time can be reduced by a factor in the range from 2.75 to 10.5 depending upon the aspect ratio of Si channels. The poly-C packaging technology, which is expected to provide new structures/concepts in MEMS/WIMS packaging, is being reported for the first time.     

A CMOS-MEMS mirror with curled-hinge comb drives

A micromirror achieves up to /spl plusmn/4.7/spl deg/ angular displacement with 18 Vdc by a comb-drive design that uses vertical angled offset of the comb fingers. Structures are made from a combination of CMOS interconnect layers and a thick underlying silicon layer. Electrical isolation of the silicon fingers is realized with a slight silicon undercut etch, which disconnects sufficiently narrow pieces of silicon under the CMOS microstructures. The 1 mm by 1 mm micromirror is made of an approximately 40 /spl mu/m-thick single-crystal silicon plate coated with aluminum from the CMOS interconnect stack. The mirror has a peak-to-peak curling of 0.5 /spl mu/m. Fabrication starts with a conventional CMOS process followed by dry-etch micromachining steps. There is no need for wafer bonding and accurate front-to-backside alignment. Such capability has potential applications in biomedical imaging, optical switches, optical scanners, interferometric systems, and vibratory gyroscopes.     

Pulsed-laser annealing, a low-thermal-budget technique for eliminating stress gradient in poly-SiGe MEMS structures

In this paper, we demonstrate eliminating the stress gradient in polycrystalline silicon germanium films at temperatures compatible with standard CMOS (Al interconnects) backend processing. First, we study the effect of varying the germanium concentration from 40% to 90%, layer thickness, deposition pressure from 650 to 800 mtorr and deposition temperature from 400 to 450/spl deg/C, on the mechanical properties of SiGe films. Then the effect of excimer laser annealing (248 nm, 38 ns, 780 mJ/cm/sup 2/) on stress gradient is analyzed. It is demonstrated that stress gradient can be eliminated completely by depositing Si/sub x/Ge/sub 1-x/(10%相似文献   

Microbridge testing on symmetrical trilayer films

In this paper, we extended the microbridge testing method to characterize the mechanical properties of symmetrical trilayer thin films. Theoretically, we analyzed the deformation of a trilayer microbridge sample with a deformable boundary condition and derived load-deflection formulas in closed-form. The slope of a load-deflection curve under small deformation gives the relationship between the bending stiffness and the residual force of a trilayer microbridge. Taking this relationship, we were able to assess simultaneously the Young's modulus of two kinds of materials composing the symmetrical trilayer film and the thickness-averaged residual stress of the film. Experimentally, we fabricated symmetrical trilayer microbridge samples of SiO/sub 2//Si/sub 3/N/sub 4//SiO/sub 2/ on 4-inch p-type (100) silicon wafers and conducted the microbridge tests with a load and displacement sensing nanoindenter system equipped with a microwedge indenter. The experimental results verified the proposed microbridge testing method. The thickness-averaged residual stress of the 1.1-/spl mu/m trilayer thin films was determined to be 8.8 MPa, while the Young's modulus of the 0.3-/spl mu/m silicon oxide layers and the Young's modulus of the 0.5-/spl mu/m silicon nitride layer were evaluated to be 31 GPa and 294 GPa, respectively.     

Fine ZnO patterning with controlled sidewall-etch front slope

This paper describes a wet-etching technique that solves the major difficulty of fine patterning a c-axis oriented polycrystalline ZnO film. The technique uses aqueous NH/sub 4/Cl with electrolytically added copper ions and convection flow, and for the first time, allows the ZnO film to be etched 1) with controlled etch rate ratio between the vertical and horizontal etch rates and 2) with controlled etch-front slope. The ratio between the vertical and horizontal etch rates is as high as 20 to 1, while the angle between the sidewall etch-front surface and the substrate surface can be electrically controlled between 73/spl deg/ and 106/spl deg/. Also, ZnO films can now be patterned to fine features (even sub-/spl mu/m level) with a wet etchant. The electroless galvanic etching technique described in this paper produces uniform etching over a large area (larger than 3" in diameter).     

Effect of trimethylsilane flow rate on the growth of SiC thin-films for fiber-optic temperature sensors

We have investigated the effect of trimethylsilane ([(CH/sub 3/)/sub 3/SiH] or 3MS) flow rate on the growth of SiC thin-film on single-crystal sapphire substrate for fiber-optic temperature sensor. The SiC film thickness was in the range of 2-3 /spl mu/m. The variation of the 3MS flow rate affected the structural properties of the SiC films. This, in turn, changed the optical properties and temperature sensing performance of the sensors. Optical reflection from the SiC thin-film Fabry-Pe/spl acute/rot interferometers showed one-way phase shifts in resonant minima on all measured samples. Linear fits to the resonant minima (at 660 to 710 nm) versus temperature provide the corresponding thermal expansion coefficient, /spl kappa//sub /spl phi//, of 1.7-1.9/spl times/10/sup -5///spl deg/C. With the optimized 3MS flow rate, the SiC temperature sensor exhibits a temperature accuracy of /spl plusmn/2.8/spl deg/C from 22 to 540/spl deg/C. The short-term SiC sensor stability at 532/spl deg/C for two weeks shows a very small standard deviation of 0.97/spl deg/C.     

Cross-linked PMMA as a low-dimensional dielectric sacrificial layer

A surface nanomachining fabrication process using electron beam cross-linked poly(methyl) methacrylate (PMMA) has been developed and characterized. PMMA with different molecular weights (MW 100 K, MW 495 K, MW 950 K) in anisole casting solvent has been crosslinked with different electron beam irradiation levels ranging from 20 C/m/sup 2/ to 240 C/m/sup 2/. This is to investigate the quantifiable relationship between electron dose and its submicrometer remaining thickness after dissolving in acetone. This technique which uses electron beam lithography, offers a high resolution semi-three-dimensional (3-D) nanomachining of the sacrificial layer in a single run. Because of its low Young's modulus, it has been successfully integrated with nanoelectromechanical systems processing and has the advantage of producing low-stress submicrometer thick structures with lateral dimensions as low as, but not limited to 1 /spl mu/m. A fast dry release time from 55 to 100 s using oxygen plasma ashing has been demonstrated for a sacrificial layer aspect ratio of 125. This corresponds to an etch rate of about 0.6 /spl mu/m/s at an average temperature of 40/spl deg/C. The success of using cross-linked PMMA as a gate dielectric is demonstrated by the fabrication of multilayered gated lateral quantum dot devices. Periodic and continuous conductance oscillations arising from Coulomb charging effects are clearly observed in the transport properties at 50 mK.     

Uncooled multimirror broad-band infrared microbolometers

A new generation of microbolometers were designed, fabricated and tested for the NASA CERES (Clouds and the Earth's Radiant Energy System) instrument to measure the radiation flux at the Earth's surface and the radiant energy now within the atmosphere. These detectors are designed to measure the earth radiances in three spectral channels consisting of a short wave channel of 0.3 to 5 /spl mu/m, a wide-band channel of 0.3 to 100 /spl mu/m and a window channel from 8 to 12 /spl mu/m each housing a 1.5 mm x 1.5 mm microbolometers or alternatively 400 /spl mu/m x 400 mm microbolometers in a 1 /spl times/ 4 array of detectors in each of the three wavelength bands, thus yielding a total of 12 channels. The microbolometers were fabricated by radio frequency (RF) magnetron sputtering at ambient temperature, using polyimide sacrificial layers and standard micromachining techniques. A semiconducting YBaCuO thermometer was employed. A double micromirror structure with multiple resonance cavities was designed to achieve a relatively uniform absorption from 0.3 to 100 /spl mu/m wavelength. Surface micromachining techniques in conjunction with a polyimide sacrificial layer were utilized to create a gap underneath the detector and the Si/sub 3/N/sub 4/ bridge layer. The temperature coefficient of resistance was measured to be -2.8%/K. The voltage responsivities were over 10/sup 3/ V/W, detectivities above 10/sup 8/ cm Hz/sup 1/2//W, noise equivalent power less than 4 /spl times/ 10/sup -10/W/Hz/sup 1/2/ and thermal time constant less than 15 ms.     

A micromachined tunable resonator fabricated by the CMOS post-process of etching silicon dioxide

This work investigates the fabrication of a micromechanical tunable resonator using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-process of only one maskless wet etching. The post-process has advantages of easy execution and low cost. The post-process employs an etchant (silox vapox III) to etch the silicon dioxide layer to release the suspended structures of the resonator. The tunable resonator comprises a driving unit, a tuning unit and a sensing unit. The resonant frequency of the resonator can be tuned using a dc-biased electrostatic comb of linearly varied finger-length. Experimental results show that the resonant frequency of the resonator is about 4.8 kHz, and it has a frequency-tuning range of 6.8% at the tuning voltage of 0–25 V.     

An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry

A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4/spl times/1.0 mm/sup 2/ proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-/spl mu/m sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end /spl Sigma/-/spl Delta/ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6/spl mu/g//spl radic/Hz in atmosphere.     

Single crystal silicon nano-wire piezoresistors for mechanical sensors

A p-type silicon (Si) nano-wire piezoresistor, whose minimum cross-sectional area is 53 nm/spl times/53 nm, was fabricated by combination of thermal diffusion, EB (electron beam) direct writing and RIE (reactive ion etching). The maximum value of longitudinal piezoresistance coefficient /spl pi//sub l[011]/ of the Si nano-wire piezoresistor was found to be 48/spl times/10/sup -5/ (1/MPa) at surface impurity concentration of 5/spl times/10/sup 19/ (cm/sup -3/) and it has enough sensitivity for mechanical sensor applications. The longitudinal piezoresistance coefficient /spl pi//sub l[011]/ of the Si nano-wire piezoresistor increased up to 60% with a decrease in the cross sectional area, while transverse piezoresistance coefficient /spl pi//sub t[011]/ decreased with a increase in the aspect ratio of the cross section. These phenomena were briefly investigated based on a hole energy consideration and FEM (finite element method) stress analysis.