共查询到20条相似文献,搜索用时 0 毫秒
1.
Dong Min Kang Ju Yeon Hong Jae Yeob Shim Jin‐Hee Lee Hyung‐Sup Yoon Kyung Ho Lee 《ETRI Journal》2005,27(2):133-139
A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band. 相似文献
2.
Dehlink B. Engl M. Aufinger K. Knapp H. 《Microwave and Wireless Components Letters, IEEE》2007,17(5):346-348
The implementation and characterization of an integrated passive bandpass filter at 77GHz is presented. A lumped elements filter occupying very small die area (110times60mum2, without pads) is demonstrated. It is realized with spiral inductors and metal-insulator-metal capacitors. The filter is fabricated in an advanced SiGe:C technology. It has a center frequency of 77.3GHz and a bandwidth of 12GHz. The insertion loss is 6.4dB. This is the first time that integrated inductors are used for filters at millimeter wave frequencies around 80GHz 相似文献
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It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz. 相似文献
4.
A novel SiGe 77 GHz sub-harmonic balanced mixer is presented with a goal to push the technology to its limit [SiGe2-RF transistor (f/sub T/=80 GHz)]. This new topology uses a compact input network not only to achieve high isolation between the LO and RF ports, but also to result in excellent 2LO-RF isolation. The measured results demonstrate a conversion gain of 0.7 dB at 77 GHz with an LO power of 10 dBm at 38 GHz, LO-RF isolation better than 30 dB, 2LO-RF isolation of 25 dB, and a P/sub 1dB/ of -8 dBm. The mixer core consumes 4.4 mA at 5 V. The circuit demonstrates that SiGe sub-harmonic mixers have comparable performance with GaAs designs, at a fraction of the cost. 相似文献
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In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave (mmW) band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier (LNA) with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply. 相似文献
6.
《Solid-State Circuits, IEEE Journal of》2008,43(10):2229-2238
This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz. 相似文献
7.
Lim K. Lee S.-H. Min S. Ock S. Hwang M.-W. Lee C.-H. Kim K.-L. Han S. 《Solid-State Circuits, IEEE Journal of》2006,41(11):2408-2416
This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements 相似文献
8.
Gunnarsson S.E. Wadefalk N. Svedin J. Cherednichenko S. Angelov I. Zirath H. Kallfass I. Leuther A. 《Microwave and Wireless Components Letters, IEEE》2008,18(4):284-286
This letter presents the design and characterization of a 220 GHz microstrip single-chip receiver monolithic microwave integrated circuit (MMIC) with an integrated antenna in a 0.1 mum GaAs metamorphic high electron mobility transistor technology. The receiver MMIC consists of a novel slot-square substrate lens feed antenna, a three-stage low noise amplifier, and a sub-harmonically pumped resistive mixer. The receiver MMIC is mounted on a 12 mm silicon substrate lens which focuses the radiation from the calibration loads to the on-chip antenna through an opening in the backside metallization of the MMIC. The double sideband noise figure of this quasioptical receiver is as low as 8.4 dB (1750 K) at 220 GHz including the losses in the antenna and in the lens. To the best of the authors' knowledge, this work demonstrates the highest integration level versus operating frequency for a MMIC ever published, regardless of technology. 相似文献
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Li-Yuan Yang Hsin-Shu Chen Chen Y.-J.E. 《Microwave and Wireless Components Letters, IEEE》2008,18(3):197-199
This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm2. Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P1 dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P1 dB is above 10% and the PAE degradation is less than 29%. 相似文献
11.
Ji Yang Shupin Huang Masatoshi Ohishi Keisuke Miyazawa Ralf Henneberger 《Journal of Infrared, Millimeter and Terahertz Waves》2001,22(2):217-223
A 492 GHz submillimeter receiver was designed for application to the POrtable Submillimeter Telescope (POST). The receiver includes a Schottky diode mixer, a phase-locked Gunn oscillator at 82.3 GHz coupled with multipliers (×2×3), and low-noise amplifiers. In this paper, the system configuration and performance will be introduced. 相似文献
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《Solid-State Circuits, IEEE Journal of》2008,43(9):1889-1896
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《Microwave and Wireless Components Letters, IEEE》2009,19(3):176-178
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《Microwave Theory and Techniques》1983,31(7):589-592
The performance of superconducting tunnel junctions as high-frequency receivers is discussed. Low-noise mixing in superconductor insulator-superconductor (SIS) quasi-particle tunnel junctions has been seen for frequencies up to 400 GHz. Such mixers have the significant advantage of small local-oscillator power requirements. A receiver has been constructed which has a single-sideband (SSB) receiver noise temperature of 305 K at 241 GHz. 相似文献
18.
This paper describes the design and performance of a low noise multicarrier receiver for a 30/20 GHz single-conversion satellite transponder. To develop a low noise receiver the following areas were examined: 1) analysis of spurious signals, 2) selection of devices most suitable for use on board the satellite, and 3) level diagram tradeoff studies. The receiver consists of a 30 GHz low noise GaAs FET amplifier, a 30/20 GHz GaAs Schottky barrier diode mixer, a dielectric resonated local oscillator, a 20 GHz high gain GaAs FET amplifier, and a 20 GHz high power (0.5 W) GaAs FET amplifier. The receiver has an 8 dB noise figure and a 48 dB gain in the frequency range from 28.395 GHz to 29.015 GHz (620 MHz frequency bandwidth). 相似文献
19.
A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS 总被引:1,自引:0,他引:1
《Solid-State Circuits, IEEE Journal of》2007,42(6):1310-1317
The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB. 相似文献
20.
使用安捷伦的ADS系统,设计一个适用于射频无线的CMOS LNA,使用0.25μm的制造工艺实现全集成化设计,工作电压为2.5 V,工作频率为2.38 GHz。重点对LNA的输入输出阻抗匹配,线性度,噪声系数,功率增益等参数进行仿真和分析。通过对电路的设计和元件的调整,设计出LNA电路的最佳性能。由仿真结果可以看出,本电路在高达20 dB功率增益的情况下,只有1.5 dB的噪声系数,并且有良好的输入输出阻抗特性。 相似文献