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1.
采用55 nm CMOS工艺设计并实现了一款用于77/79 GHz汽车雷达的宽带功率放大器。设计了一个大尺寸的W波段功率单元,优化功率单元内部结构及外部无源器件连接方法,减少了功率单元的寄生电容、电感和电阻。采用一种将晶体管寄生电容考虑在内的变压器耦合谐振峰值控制技术,提高了功放的增益及带宽。在共源共栅结构基础上,采用了一种共栅短路技术,提升输出功率并改善功放稳定性。测试结果表明,该功率放大器具有良好的输入、输出匹配性能,3 dB带宽达到9 GHz,饱和输出功率达到15.5 dBm,峰值效率达到12.5%,实现了优异的FOM值。  相似文献   

2.
A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.  相似文献   

3.
综合评述了硅基77 GHz汽车雷达收发芯片的技术背景、研究现状以及面临的挑战。首先,介绍了毫米波汽车雷达的频谱划分、制作工艺和雷达体制选择。在此基础上,总结分析了近十年汽车雷达收发芯片领域的技术演进和发展趋势,分别介绍了SiGe工艺和CMOS工艺下77 GHz雷达收发芯片以及最新毫米波电路技术。最后,提出了毫米波汽车雷达芯片所面临的挑战。  相似文献   

4.
The implementation and characterization of an integrated passive bandpass filter at 77GHz is presented. A lumped elements filter occupying very small die area (110times60mum2, without pads) is demonstrated. It is realized with spiral inductors and metal-insulator-metal capacitors. The filter is fabricated in an advanced SiGe:C technology. It has a center frequency of 77.3GHz and a bandwidth of 12GHz. The insertion loss is 6.4dB. This is the first time that integrated inductors are used for filters at millimeter wave frequencies around 80GHz  相似文献   

5.
It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz.  相似文献   

6.
A novel SiGe 77 GHz sub-harmonic balanced mixer is presented with a goal to push the technology to its limit [SiGe2-RF transistor (f/sub T/=80 GHz)]. This new topology uses a compact input network not only to achieve high isolation between the LO and RF ports, but also to result in excellent 2LO-RF isolation. The measured results demonstrate a conversion gain of 0.7 dB at 77 GHz with an LO power of 10 dBm at 38 GHz, LO-RF isolation better than 30 dB, 2LO-RF isolation of 25 dB, and a P/sub 1dB/ of -8 dBm. The mixer core consumes 4.4 mA at 5 V. The circuit demonstrates that SiGe sub-harmonic mixers have comparable performance with GaAs designs, at a fraction of the cost.  相似文献   

7.
In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave (mmW) band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier (LNA) with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.  相似文献   

8.
This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.  相似文献   

9.
针对未来智能驾驶和无人驾驶对毫米波传感器多模式、多场景感知需求,设计并实现了一种77GHz多模毫米波雷达收发机芯片。芯片采用65nm CMOS工艺,集成了3路雷达发射机和4路接收机、调频连续波(FMCW)波形发生器、模数转换器以及高速数据接口等电路。利用交叉耦合中和电容技术提升了CMOS工艺上毫米波低噪声放大器、毫米波片上功放等电路性能,采用两点调制锁相环技术提升了FMCW信号带宽和调制速率。收发机的发射功率、波形样式、接收增益和带宽等参数具有较好的可配置性,满足未来多模式、小型化和低成本汽车雷达传感器需求。芯片测试结果显示,在76~81GHz频率范围内,接收机实现50dB的增益控制,最小噪声系数11dB,FMCW信号调频带宽达4.2GHz,调制速率达233MHz/μs,线性度优于0.1%,-45~+125℃全温范围内发射机典型输出功率大于13dBm。  相似文献   

10.
This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements  相似文献   

11.
This letter presents the design and characterization of a 220 GHz microstrip single-chip receiver monolithic microwave integrated circuit (MMIC) with an integrated antenna in a 0.1 mum GaAs metamorphic high electron mobility transistor technology. The receiver MMIC consists of a novel slot-square substrate lens feed antenna, a three-stage low noise amplifier, and a sub-harmonically pumped resistive mixer. The receiver MMIC is mounted on a 12 mm silicon substrate lens which focuses the radiation from the calibration loads to the on-chip antenna through an opening in the backside metallization of the MMIC. The double sideband noise figure of this quasioptical receiver is as low as 8.4 dB (1750 K) at 220 GHz including the losses in the antenna and in the lens. To the best of the authors' knowledge, this work demonstrates the highest integration level versus operating frequency for a MMIC ever published, regardless of technology.  相似文献   

12.
实现了一个带宽和增益可配置、高线性度、低噪声的模拟基带电路,可应用于77 GHzCMOS毫米波雷达接收机.电路包括一个带宽可配置的5阶巴特沃斯低通滤波器模块、三个可编程增益放大器模块以及三个直流失调消除环路.增益范围为18~70 dB,增益步进为6 dB;带宽为200 kHz~2 MHz;噪声系数最小为24 dB;输出1-dB压缩点为5.1 dBm,在最高增益时,IIP3为-52dBm;功耗为14.6 mA@1 V.电路采用65 nm CMOS工艺实现,芯片面积为1.2×0.93 (mm2).  相似文献   

13.
采用0.18μm CMOS工艺设计并制作了一个2.4 GHz全集成CMOS Doherty功率放大器.着重考虑了片上螺旋电感的回流路径对电感模型的影响,并在设计中使用了一种新颖的螺旋电感版图结构来避免回流路径的影响.实测结果表明该功率放大器增益达到16dB,1dB压缩点为20.5dBm,峰值输出功率和对应功率附加效率分别为21.2dBm和20.4%,整个芯片面积为2.8mm×1.7mm.  相似文献   

14.
本文对调频副载波(SCA)广播接收机的单片化设计进行了探讨,提出了一种新的适合CMOS工艺的全集成SCA接收机结构。接收机采用Weaver-零中频结构实现下变频和二次解调功能,节省了片外镜像抑制滤波器,大大提高了接收机的集成度,降低了接收机的成本和功耗,显示了广阔的潜在应用前景。  相似文献   

15.
This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm2. Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P1 dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P1 dB is above 10% and the PAE degradation is less than 29%.  相似文献   

16.
1OGb/s SiGe光接收机限幅放大器   总被引:1,自引:0,他引:1  
给出了一个利用IBM 0.5μm SiGe BiCMOS工艺实现的10Gb/s限幅放大器.在标准的3.3V电源电压,功耗为133.77mW.在31dB的输入动态范围内,可以保持980mVpp恒定输出摆幅.  相似文献   

17.
A second-order, single-ended, fully integrated low- pass filter with cut-off frequency tunable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology, combining Gm values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The circuit has been designed and fabricated using 3.3-V 0.35-mum CMOS devices from the STMicroelectronics Bipolar-CMOS-DMOS process BCD6. The tested prototype occupies an area of 960 x 350 mum2 and requires a supply current ranging from 50 to 500 muLambda, depending on tuning. Total harmonic distortion lower than 1% has been measured in a wide tuning range for 1-V peak-to-peak input signal amplitude. The effect of temperature on the tuning law in the interval 0-80degC is shown. A dynamic range in excess of 60 dB over the whole tuning range has been estimated from distortion and noise measurements.  相似文献   

18.
数字接收机是数字阵雷达系统的核心模块之一,其性能指标影响整部雷达的目标探测性能。文中介绍一种运用于高机动车载雷达平台的多通道一体化数字接收机,其采用一种全新的小型化、模块化、高度集成化的设计方案。一体化接收机采用收发全数字集成化设计,收发信号形式和波形设计非常灵活;对外接口简单,体积小、质量轻、集成度高,电磁兼容性好,并具备在强振动冲击条件下持续工作的能力。  相似文献   

19.
提出了一种频率可调范围约230MHz的全集成LC压控振荡器(VCO).该压控振荡器是用6层金属、0.18μm的标准CMOS工艺制造完成.采用MOS晶体管和电容组合来实现等效变容管,为降低芯片面积仅使用一个片上螺旋电感,并实施了低电压、低功耗的措施.测试结果表明,该压控振荡器在电源电压为1.8V的情况下功耗约为10mW,在振荡器中心频率为2.46GHz时的单边带相位噪声为-105.89dBc/Hz@600kHz.该压控振荡器可以应用于锁相环电路或频率综合器中.  相似文献   

20.
一种适用于2 4GHz ISM射频波段的全集成CMOS压控振荡器   总被引:8,自引:2,他引:6  
提出了一种频率可调范围约 2 30MHz的全集成LC压控振荡器 (VCO) .该压控振荡器是用 6层金属、0 18μm的标准CMOS工艺制造完成 .采用MOS晶体管和电容组合来实现等效变容管 ,为降低芯片面积仅使用一个片上螺旋电感 ,并实施了低电压、低功耗的措施 .测试结果表明 ,该压控振荡器在电源电压为 1 8V的情况下功耗约为10mW ,在振荡器中心频率为 2 46GHz时的单边带相位噪声为 - 10 5 89dBc/Hz @6 0 0kHz .该压控振荡器可以应用于锁相环电路或频率综合器中.  相似文献   

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