A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

Integrated Bandpass Filter at 77 GHz in SiGe Technology

The implementation and characterization of an integrated passive bandpass filter at 77GHz is presented. A lumped elements filter occupying very small die area (110times60mum², without pads) is demonstrated. It is realized with spiral inductors and metal-insulator-metal capacitors. The filter is fabricated in an advanced SiGe:C technology. It has a center frequency of 77.3GHz and a bandwidth of 12GHz. The insertion loss is 6.4dB. This is the first time that integrated inductors are used for filters at millimeter wave frequencies around 80GHz     

Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz

It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz.     

A 77 GHz SiGe sub-harmonic balanced mixer

A novel SiGe 77 GHz sub-harmonic balanced mixer is presented with a goal to push the technology to its limit [SiGe2-RF transistor (f/sub T/=80 GHz)]. This new topology uses a compact input network not only to achieve high isolation between the LO and RF ports, but also to result in excellent 2LO-RF isolation. The measured results demonstrate a conversion gain of 0.7 dB at 77 GHz with an LO power of 10 dBm at 38 GHz, LO-RF isolation better than 30 dB, 2LO-RF isolation of 25 dB, and a P/sub 1dB/ of -8 dBm. The mixer core consumes 4.4 mA at 5 V. The circuit demonstrates that SiGe sub-harmonic mixers have comparable performance with GaAs designs, at a fraction of the cost.     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements     

A 220 GHz Single-Chip Receiver MMIC With Integrated Antenna

This letter presents the design and characterization of a 220 GHz microstrip single-chip receiver monolithic microwave integrated circuit (MMIC) with an integrated antenna in a 0.1 mum GaAs metamorphic high electron mobility transistor technology. The receiver MMIC consists of a novel slot-square substrate lens feed antenna, a three-stage low noise amplifier, and a sub-harmonically pumped resistive mixer. The receiver MMIC is mounted on a 12 mm silicon substrate lens which focuses the radiation from the calibration loads to the on-chip antenna through an opening in the backside metallization of the MMIC. The double sideband noise figure of this quasioptical receiver is as low as 8.4 dB (1750 K) at 220 GHz including the losses in the antenna and in the lens. To the best of the authors' knowledge, this work demonstrates the highest integration level versus operating frequency for a MMIC ever published, regardless of technology.     

全集成CMOS SCA接收机单片化探讨

本文对调频副载波(SCA)广播接收机的单片化设计进行了探讨,提出了一种新的适合CMOS工艺的全集成SCA接收机结构。接收机采用Weaver-零中频结构实现下变频和二次解调功能,节省了片外镜像抑制滤波器,大大提高了接收机的集成度,降低了接收机的成本和功耗,显示了广阔的潜在应用前景。     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

A 492 GHz Submillimeter-Wave Receiver

A 492 GHz submillimeter receiver was designed for application to the POrtable Submillimeter Telescope (POST). The receiver includes a Schottky diode mixer, a phase-locked Gunn oscillator at 82.3 GHz coupled with multipliers (×2×3), and low-noise amplifiers. In this paper, the system configuration and performance will be introduced.     

雷达接收机综合测试系统研究

雷达接收机参数综合测试系统采用可编程逻辑器件,简化了电路结构,增强了系统设计的灵活性和可靠性,降低了体积与成本。应用表明,该系统能对雷达接收机进行自动测试和分析,大大加快了雷达系统的研制进度。     

A Silicon-Germanium Receiver for X-Band Transmit/Receive Radar Modules

This work investigates the potential of commercially-available silicon-germanium (SiGe) BiCMOS technology for X-band transmit/receive (T/R) radar modules, focusing on the receiver section of the module. A 5-bit receiver operating from 8 to 10.7 GHz is presented, demonstrating a gain of 11 dB, and average noise figure of 4.1 dB, and an input-referred third-order intercept point $({hbox{IIP}}_{3})$ of $-$13 dBm, while only dissipating 33 mW of power. The receiver is capable of providing 32 distinct phase states from 0 to 360$^{circ}$ , with an rms phase error $≪ !{hbox{9}}^{circ}$ and an rms gain error $≪ ,$0.6 dB. This level of circuit performance and integration capability demonstrates the benefits of SiGe BiCMOS technology for emerging radar applications, making it an excellent candidate for integrated X-band phased-array radar transmit/receive modules.      

2.45 GHz全集成CMOS功率放大器设计

在一个RF收发机系统中,功率放大器的集成问题一直是难点之一.首先简要介绍开关模式功率放大器及其提高效率的理论基础,然后采用0.18 μm CMOS工艺给出了工作在2.45 GHz的全集成单片功率放大器的设计,并采用ADS仿真软件验证了设计的正确性.     

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

全集成2.4 GHz CMOS对称式收发开关的设计

文章设计了一种应用于无线通信的2．4GHz全集成对称式串并型射频收发开关，详细分析了影响这种射频收发开关性能的各种因素，并采用了相应的优化方案。经仿真，在2．5V电压下获得了插入损耗1．0dB、隔离度30．5dB和1dB压缩点为16．1dBm的较好结果。该开关采用TSMC0．25μm工艺设计实现，版图面积(包括pad)为0．6mm^2。     

A Superconducting Tunnel Junction Receiver for 230 GHz

The performance of superconducting tunnel junctions as high-frequency receivers is discussed. Low-noise mixing in superconductor insulator-superconductor (SIS) quasi-particle tunnel junctions has been seen for frequencies up to 400 GHz. Such mixers have the significant advantage of small local-oscillator power requirements. A receiver has been constructed which has a single-sideband (SSB) receiver noise temperature of 305 K at 241 GHz.     

30 GHz Band Low Noise Receiver for 30/20 GHz Single-Conversion Transponder

This paper describes the design and performance of a low noise multicarrier receiver for a 30/20 GHz single-conversion satellite transponder. To develop a low noise receiver the following areas were examined: 1) analysis of spurious signals, 2) selection of devices most suitable for use on board the satellite, and 3) level diagram tradeoff studies. The receiver consists of a 30 GHz low noise GaAs FET amplifier, a 30/20 GHz GaAs Schottky barrier diode mixer, a dielectric resonated local oscillator, a 20 GHz high gain GaAs FET amplifier, and a 20 GHz high power (0.5 W) GaAs FET amplifier. The receiver has an 8 dB noise figure and a 48 dB gain in the frequency range from 28.395 GHz to 29.015 GHz (620 MHz frequency bandwidth).     

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB.     

用ADS实现一个2．38GHz全集成化低噪声放大器设计

使用安捷伦的ADS系统,设计一个适用于射频无线的CMOS LNA,使用0.25μm的制造工艺实现全集成化设计,工作电压为2.5 V,工作频率为2.38 GHz。重点对LNA的输入输出阻抗匹配,线性度,噪声系数,功率增益等参数进行仿真和分析。通过对电路的设计和元件的调整,设计出LNA电路的最佳性能。由仿真结果可以看出,本电路在高达20 dB功率增益的情况下,只有1.5 dB的噪声系数,并且有良好的输入输出阻抗特性。