倒装片封装与芯片规模封装的综合比较及其发展前景

本文主要论述了现代微电子封装技术中倒装片封装技术和芯片规模封装技术的结构类型,应用产品,倒装片与晶片级规模封装,并阐述了倒装片封装与芯片规模封装的综合比较及其发展前景。     

倒装芯片键合技术发展现状与展望

我国集成电路发展十二五规划中提到,大力发展先进封装和测试技术,推进高密度堆叠型三维封装产品的进程,支持封装工艺技术升级和产能扩充。阐述了先进封装技术中的倒装芯片键合工艺现状及发展趋势,以及国际主流倒装设备发展及国内应用现状,重点介绍了北京中电科装备有限公司的倒装机产品。国产电子装备厂商应认清回流焊倒装芯片键合设备市场发展,缩短倒装设备产品开发周期和推向市场的时间,奠定国产电子先进封装设备产业化基础;同时抓紧研发细间距铜柱凸点倒装和热压焊接技术,迎接热压倒装芯片工艺及其设备的挑战。     

倒装芯片焊点可靠性的有限元模拟法探讨

随着集成电路封装技术的发展,倒装芯片技术得到广泛应用.由于材料的热膨胀失配,使倒装焊点成为芯片封装中失效率最高的部位,而利用快捷又极具参考价值的有限元模拟法是研究焊点可靠性的重要手段之一.简单介绍了集成电路芯片焊点可靠性分析的有限元模拟法,重点概括了利用该方法对芯片焊点进行可靠性评价常见的材料性质和疲劳寿命预测模型.     

微电子封装中芯片焊接技术及其设备的发展

概述了微电子封装中引线键合、载带自动键合、倒装芯片焊料焊凸键合、倒装芯片微型焊凸键合等芯片焊接技术及其设备的发展 ,同时报告了世界著名封装设备制造公司芯片焊接设备的现状及发展趋势。     

芯片封装互连新工艺热超声倒装焊的发展现状

介绍了一种芯片封装互连新工艺热超声倒装芯片连接工艺.在比较当前多种芯片封装方式的基础上,总结了这一工艺的特点及优越性,并详细论述了当前这一工艺的技术进展与理论研究状况,指出该工艺是芯片封装领域中具有发展潜力的新工艺.     

高压倒装LED照明组件的热性能

高压(HX)倒装LED是一种新型的光源器件,在小尺寸、高功率密度发光光源领域有广泛的应用前景.设计了4种不同工作电压的高压倒装LED芯片,进行了流片验证,并对其进行了免封装芯片(PFC)结构的封装实验,在其基础上研制出一种基于高压倒装芯片的PFC-LED照明组件.建立了9V高压倒装LED芯片、PFC封装器件及照明组件的模型,利用流体力学分析软件进行了热学模拟和优化设计;利用T3Ster热阻测试分析仪进行了热阻测试,验证了设计的可行性.结果表明,基于9V高压倒装LED芯片的PFC封装器件的热阻约为0.342 K/W,远小于普通正装LED器件的热阻.实验结果为基于高压倒装LED芯片的封装及应用提供了热学设计依据.     

超级CSP——一种晶圆片级封装

研究了圆片级芯片尺寸封装.使用再分布技术的圆片级封装制作了倒装芯片面阵列.如果用下填充技术,在再分布层里和焊结处的热疲劳应力可以减小,使倒装芯片组装获得大的可靠性.     

倒装片可修复底部填充材料的研究现状及发展

有机基板上的倒装芯片一般采用底部填充技术以提高其封装的可靠性.有缺陷的芯片在倒装后难以进行返工替换,使得倒装芯片技术成本提高,限制了此技术的应用.提出新型可修复底部填充材料的开发成为解决这一问题的有效途径.介绍了倒装芯片的可修复底部填充技术和可应用于可修复底部填充材料的技术要求,并综述了国内外对于可修复底部填充材料的研究现状.     

适合于印刷工艺的IndiumTacflux676助焊剂在倒装芯片装配过程中的应用

倒装芯片是一种无弓1脚结构的芯片互联技术,它起源于60年代,由IBM率先研发,具体原理是在I／O板上沉积焊料凸点,然后将芯片翻转加热利用熔融的焊料凸点与基板相结合,此技术代替了常规的打线接合,在封装技术的应用范围日益广泛,己逐步成为高端器件及高密度封装领域中经常采用的封装形式,特别是它可以采用类似SMT技术（印刷）的手段来加工生产效率将有大幅的提升,因此倒装芯片封装技术将是高密度芯片封装的最终方向。     

倒装芯片封装器件开封方法研究

对倒装芯片封装(Flip-Chip Package)器件开封技术进行了研究。总结了倒装芯片封装的类型、结构和封装材料；从理论上证明了倒装芯片封装器件开封的可能,并找出了限制开封的制约因素；提出了一种倒装芯片封装器件开封方法,通过X射线检查、镶嵌、磨抛和酸刻蚀的综合应用,突破了限制这类器件开封的因素,并证明了该方法的适用性；给出了建议的试验条件,并展示了开封效果。     

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

利用声音微图像进行PCB检测

由于在印制电路板上的倒装芯片和CSP器件的紧凑设计,声音微图像己经成为检测这些封装的非常重要的一部分。     

A novel approach for flip chip solder joint quality inspection:laser ultrasound and interferometric system

A novel, noncontact, nondestructive approach for flip chip solder joint quality inspection is presented. In this technique, a pulsed laser generates ultrasound on the chip's surface, exciting the whole chip into a vibration motion. An interferometer was used to measure the vibration displacement of the chip's surface. Because changes in solder joint quality produce a different vibration response, a value, "error ratio," is used to measure the difference between a good chip and a chip with defects. An automatic signal-processing algorithm to calculate the error ratio was developed and implemented, as well as a frequency analysis algorithm. The inspection system was characterized, and results are presented for two cases of flip chips with missing solder balls. Results indicate that a laser ultrasonic/interferometeric system offers great promise for solder bump inspection in flip chip, BGA, chip scale, and micro BGA packages     

Dynamic strength of anisotropic conductive joints in flip chip on glass and flip chip on flex packages

The work presented in this paper focuses on the behavior of anisotropically conductive film (ACF) joint under the dynamic loading of flip chip on glass (COG) and flip chip on flexible (COF) substrate packages. Impact tests were performed to investigate the key factors that affect the adhesion strength. Scanning electron microscopy (SEM) was used to evaluate the fractography characteristics of the fracture. Impact strength increased with the bonding temperature, but after a certain temperature, it decreased. Good absorption and higher degree of curing at higher bonding temperature accounts for the increase of the adhesion strength, while too high temperature causes overcuring of ACF and degradation at ACF/substrate interface––thus decreases the adhesion strength. Higher extent of air bubbles was found at the ACF/substrate interface of the sample bonded at the higher temperature. These air bubbles reduce the actual contact area and hence reduce the impact strength. Although bonding pressure was not found to influence the impact strength significantly, it is still important for a reliable electrical interconnect. The behaviors of the conductive particles during impact loading were also studied. From the fracture mode study, it was found that impact load caused fracture to propagate in the ACF/substrate interface (for COG packages), and in the ACF matrix (for COF packages). Because of weak interaction of the ACF with the glass, COG showed poor impact adhesion.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Flip chip on board: assessment of reliability in cellular phone application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.     

A novel flip chip technology using nonconductive resin sheet

The process flow of this new packaging system is as follows. First, epoxy base resin sheet is laminated onto substrate to cover the substrate surface including land electrodes. Bumped chip alignment and attachment was done through the resin sheet, in the second stage with pressure and temperature. The bumps under the chip penetrate with removal of resin sheet material eventually reaching to the metal land of the substrate in this process. Metal connection and curing of the interface resin have been completed in the third stage. This new process has the potential to make flip chip packages simple compared with the current process using liquid resin with dispensing system. The throughput time can be reduced to less than 10 s/unit in actual model case even for large flip chip package which has over 15×15 (mm) square area IC chips. The other advantages are thermal stability of material in the process, moisture related performance, and warpage control performance. For current underfill process the only choice is to use anhydride type resin system which has many disadvantages. This new process made it possible to introduce moisture and thermally stable epoxy resin with phenol curing system for flip chip packaging. Drastic process ability improvement can be achieved by the new process and material. As a typical improvement of thermal shock performance, it was confirmed that the life of chip damage is over 10 times longer by flip chip bonding parameters which can be controlled only by this new flip chip packaging process