高速低功耗自适应可编程分频器

在约翰逊计数分频器的基础上,设计了一款双级结构分频器,采用系数自适应分配技术,显著提升了分频器的工作频率,并有效降低功耗。基于45nm CMOS工艺进行仿真,结果表明:该分频器最高工作频率可达8GHz,在1GHz时,49分频的双级可编程分频器功耗仅为63μW,在8GHz时,功耗为312μW。与典型的约翰逊结构相比,双级分频器工作频率可提升1.6倍,在分频器系数设置为6时,最大功耗优化比达到51.82%。     

基于FPGA的音响系统数字分频器

比较了数字分频器与传统模拟分频器,说明数字分频器更具优点.采用FPGA芯片实现一个音响系统的数字分频器,并详细描述了该系统的组成及各部分的实现方法,最后给出实际使用效果.     

基于0.13 μm CMOS工艺的低电压高速1:2分频器设计

在光纤传输系统中,分频器是工作在最高频率的电路之一,起着至关重要的作用,本文就采用了由锁存器构成的数字1:2分频器.采用UMC 0.13μm CMOS工艺,设计了电源电压为1V,工作频率范围为5～20GHz的1:2分频器电路.该电路由基本分频器单元以及输入输出缓冲组成.基本分频器单元采用单端动态负载锁存器.整体电路功耗...     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

0.35μm CMOS 8.5GHz 1∶8分频器的设计

实现了一个基于触发器结构用0.35μm CMOS工艺实现的1∶8分频器.它由3级1∶2 分频器单元组成,其中第一级为动态分频器,决定了整个芯片的性能,第二、三级为静态分频器,在低频下能稳定工作.分频器采用源极耦合逻辑电路,并在传统的电路结构上进行改进,提高了电路的性能.测试的结果表明,芯片工作速率超过8.5GHz,工作带宽大于2GHz.电路在3.3V电源电压下工作,每个1∶2分频器单元的功耗约为11mW,面积为35μm×50μm.该芯片可应用于高速射频或光电收发机系统中.     

一种新型高速低功耗BiCMOS分频器

本文设计了一种基于BiCMOS技术的分频器,结合了双极（Bipolar）和CMOS技术的优点。作为分频器的基本单元,锁存器的工作速度直接影响了分频器的性能。通过分离跟踪差分对与交叉耦合对,并减小后者的偏置电流可以提高锁存器的工作速度。同时,合并两个锁存器的跟踪差分对可以减小分频器的功耗。采用0．8μm BiCMOS模型在Cadence SPECTRE中仿真,可以得到这种新型高速低功耗分频器的工作频率上限可以达到2．4GHz,功耗为-1．61dBm。     

0.35μm CMOS 8 5GHz1∶8分频器的设计

实现了一个基于触发器结构用 0 .35μm CMOS工艺实现的 1∶ 8分频器 .它由 3级 1∶ 2分频器单元组成 ,其中第一级为动态分频器 ,决定了整个芯片的性能 ,第二、三级为静态分频器 ,在低频下能稳定工作 .分频器采用源极耦合逻辑电路 ,并在传统的电路结构上进行改进 ,提高了电路的性能 .测试的结果表明 ,芯片工作速率超过8.5 GHz,工作带宽大于 2 GHz.电路在 3.3V电源电压下工作 ,每个 1∶ 2分频器单元的功耗约为 11m W,面积为35μm× 5 0μm .该芯片可应用于高速射频或光电收发机系统中     

国外硅双极分频器发展概况

本文综述了国外近十年来超高速分频器集成电路的发展概况。着重介绍了反馈分频方式的原理。并叙述了采用几种先进硅双极工艺(如SST、SICOS、BSA等)制作的反馈分频方式的分频器和主从D触发器方式的分频器。最后简单介绍了超高速分频器的应用情况。     

一种1.8 V 4.8 GHz 0.9 mW 0.18 μm CMOS分频器

给出了一个电源电压为1.8 V、功耗为0.9 mW的4.8 GHz二分频器。该分频器采用基于反转触发器(TFF)的电路结构,使用动态负载,输出I、Q两路正交信号。对设计的电路采用标准UMC 0.18μm CMOS工艺进行了仿真,结果表明,该分频器工作频率可达6.5 GHz。     

W波段InGaAs/InP动态二分频器

采用fT=214 GHz,fmax=193 GHz的InGaAs/InP异质结双极型晶体管工艺,设计了一款基于时钟驱动型反相器的动态二分频器.该分频器工作频段为60 ～ 100 GHz,但由于测试系统上限频率的限制,只能测出62 ～ 83 GHz的工作范围.在-4.2V和-5.2 V的单电源直流偏置下该分频器的功耗分别为596.4 mW、1060.8 mW.此分频器的成功制作对于工作在W波段锁相环的构建有较大的意义.     

39.5-GHz static frequency divider implemented in AlInAs/GaInAs HBTtechnology

A static divide-by-4 frequency divider operating at 39.5 GHz with a corresponding gate delay of 12.6 ps was implemented using InP-based HBT technology. The AlInAs/GaInAs HBT devices utilized in the divider incorporated a graded emitter-base (E-B) junction and had a unity gain cutoff frequency, maximum frequency of oscillation, and current gain β of 130 GHz, 91 GHz, and 39, respectively. The divider was operated with a 3-V power supply and consumed a total power of 425 mW (77 mW per flip-flop). The divider functional yield was over 90%. The operating frequency of this circuit is the highest ever reported for a static divider     

75 GHz ECL static frequency divider using InAlAs/InGaAs HBTs

A 75 GHz static frequency divider in InAlAs/InGaAs transferred-substrate heterojunction bipolar transistor (HBT) technology is reported. This is the highest reported frequency of operation for a static frequency divider. The circuit has 60 transistors and dissipates 800 mW. The divider was operated at a clock frequency of 5.0 to 75 GHz     

SZ541和SZ551型GaAs高速分频器

本文叙述了SZ541和SZ551分频器工作原理、电路设计和制作工艺技术。电路采用全离子注入平面工艺,L_g为0.6～0.8μm.SZ541GaAs静态分频器可从DC到3GHz工作。SZ551GaAs动态分频器工作带宽为0.5～4.5GHz。     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider

We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f/sub T//2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.     

A Wide Locking-Range Frequency Divider for LMDS Applications

A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications.     

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.     

58.8/39.2 GHz dual-modulus CMOS frequency divider with 9.2x5.2 /spl mu/m core size

A 58.8/39.2 GHz dual-modulus inductor-less frequency divider is proposed. The divider was fabricated using 90 nm CMOS with 9.2times5.2 mum core size. As a result, without using an inductor, the operating frequency was 40 GHz in the divide-by-2 mode and 59 GHz in the divide-by-3 mode at a power-supply voltage of 1.15 V with a power consumption of 1.2 mW     

A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

A low power divide-by-8 injection-locked frequency divider is presented. The frequency divider consists of four current-mode logic (CML) D-latches connected in the form of a four-stage ring with the differential input signal injected into the clock terminals of the latches. The output signals can be taken from the data terminals of any of the four latches. The proposed frequency divider has higher operating frequency and lower power dissipation compared with conventional static frequency dividers. Compared with existing injection-locked frequency dividers, the proposed fully differential frequency divider presents wider locking range with the center frequency independent of injection amplitude. The frequency divider is implemented in TSMC 0.18 mum CMOS technology. It consumes around 3.6 mW power with 1.8 V supply. The operating frequency can be tuned from 4 GHz to 18 GHz. The ratio of the locking range over the center frequency is up to 50% depending on the operating frequency and biasing conditions