基于分离位线DICE结构的SRAM存储单元版图抗辐射设计

在SRAM加固设计中,存储单元的版图抗辐射设计起着重要的作用。基于分离位线的双互锁存储单元（DICE）结构,采用0.18μm体硅工艺,根据电路功能、结构和抗辐射性能,设计了一种新的NMOS隔离管的SRAM存储单元版图结构。根据分析结果,SRAM存储单元在确保存储单元功能的前提下,具备抗总剂量效应、抗单粒子翻转和抗单粒子闩锁效应,同时可实现单元面积的最优化。     

一种新型低功耗加固SRAM存储单元

提出了一种抗辐射加固12T SRAM存储单元.采用NMOS管组成的堆栈结构降低功耗,利用单粒子翻转特性来减少敏感节点,获得了良好的可靠性和低功耗.Hspice仿真结果表明,该加固SRAM存储单元能够完全容忍单点翻转,容忍双点翻转比例为33.33％.与其他10种存储单元相比,该存储单元的面积开销平均增加了 3.90％,功...     

电离总剂量辐射加固SRAM设计

在空间和核辐射环境下,电离总剂量辐射(TID)效应严重影响采用商用CMOS工艺的SRAM的可靠性和寿命.针对SRAM,设计了四种TID加固的存储单元,分析对比了四个加固单元对TID,单粒子闩锁、单粒子翻转三种SRAM中常见辐射效应的抵御水平以及加固单元的面积和速度.加固SRAM单元的抗TID水平得到极大提高,同时,抗单粒子效应水平、面积、速度也达到一定的要求.这些单元可用于实现基于商用CMOS工艺并具有高抗辐射性能的SRAM.     

低功耗容软错误的65 nm CMOS 12管SRAM单元

提出了一种具有软错误自恢复能力的12管SRAM单元。该单元省去了专用的存取管,具有高鲁棒性、低功耗的优点。在65 nm CMOS工艺下,该结构能够完全容忍单点翻转,容忍双点翻转的比例是64.29%,与DICE加固单元相比,双点翻转率降低了30.96%。与DICE、Quatro等相关SRAM加固单元相比,该SRAM单元的读操作电流平均下降了77.91%,动态功耗平均下降了60.21%,静态电流平均下降了44.60%,亚阈值泄漏电流平均下降了27.49%,适用于低功耗场合。     

抗单粒子翻转效应的SRAM研究与设计

在空间应用和核辐射环境中,单粒子翻转(SEU)效应严重影响SRAM的可靠性。采用错误检测与校正(EDAC)和版图设计加固技术研究和设计了一款抗辐射SRAM芯片,以提高SRAM的抗单粒子翻转效应能力。内置的EDAC模块不仅实现了对存储数据"纠一检二"的功能,其附加的存储数据错误标志位还简化了SRAM的测试方案。通过SRAM原型芯片的流片和测试,验证了EDAC电路的功能。与三模冗余技术相比,所设计的抗辐射SRAM芯片具有面积小、集成度高以及低功耗等优点。     

用SOI技术提高CMOS SRAM的抗单粒子翻转能力

提高静态随机存储器（SRAM）的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅（SOI）基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61．8MeV／（mg／cm^2）,优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。     

一种多模式SRAM单粒子试验系统的设计与实现

提出了一种基于NIOS II的异步SRAM单粒子效应检测系统,用于评估抗辐射加固SRAM电路的抗单粒子效应能力.该检测系统可以对异步SRAM进行四种工作模式下的动态和静态检测,利用该检测系统在重离子加速器上对一款异步SRAM进行了单粒子效应试验,获得了5种离子的试验数据,统计分析后得到了器件的单粒子翻转阈值、单粒子翻转饱和截面和单粒子翻转在轨错误率,并与国外同款电路进行了对比,最后依据试验结果给出了评估结论.     

一种全nMOS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管. 存取管的沟道长度小于下拉管的沟道长度. 由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑“1" . 存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的“读”操作. 背栅反馈同时增强了SRAM单元的静态噪声容限(SNM). 该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积. 对SRAM单元的读写速度和功耗做了仿真和讨论. 该SRAM单元可以工作在0.5V电源电压下.     

一种全nMoS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管.存取管的沟道长度小于下拉管的沟道长度.由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑"1".存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的"读"操作.背栅反馈同时增强了SRAM单元的静态噪声容限(SNM).该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积.对SRAM单元的读写速度和功耗做了仿真和讨论.该SRAM单元可以工作在0.5V电源电压下.     

基于0.18 μm CMOS加固工艺的抗辐射单元库开发

抗辐射单元库是快速完成抗辐射数字电路设计的基础.基于0.18μmCMOS加固工艺总剂量及单粒子效应加固策略,从单元库规格制定、逻辑与版图设计、单元库特征参数提取及布局布线文件抽取、单元库设计套件质量保证到最终硅验证,完成了抗辐射单元库的全流程开发.抗辐射单元库在速度、面积、功耗及抗辐射性能4个方面表现出良好的均衡性,具...     

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.     

TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme.      

一种面向可容错应用的低功耗SRAM架构

提出了一种面向可容错应用的低功耗SRAM架构。通过对输入数据进行预编码,提出的SRAM架构实现了以较小的精度损失降低SRAM电路功耗。设计了一种单端的8管SRAM单元。该8管单元采用读缓冲结构,提升了读稳定性。采用打破反馈环技术,提升了写能力。以该8管单元作为存储单元的近似SRAM电路能够在超低压下稳定工作。在40 nm CMOS工艺下对电路进行仿真。结果表明,该8管单元具有良好的稳定性和极低的功耗。因此,以该8管单元作为存储单元的近似SRAM电路具有非常低的功耗。在0.5 V电源电压和相同工作频率下,该近似SRAM电路的功耗比采用传统6管单元的SRAM电路功耗降低了59.86%。     

一种基于位交错结构的亚阈值10管SRAM单元

提出了一种基于位交错结构的亚阈值10管SRAM单元,实现了电路在超低电压下能稳定地工作,并降低了电路功耗。采用内在读辅助技术消除了读干扰问题,有效提高了低压下的读稳定性。采用削弱单元反馈环路的写辅助技术,极大提高了写能力。该10管SRAM单元可消除半选干扰问题,提高位交错结构的抗软错误能力。在40 nm CMOS工艺下对电路进行了仿真。结果表明,该10管SRAM单元在低压下具有较高的读稳定性和优异的写能力。在0.4 V工作电压下,该10管SRAM单元的写裕度为传统6管单元的14.55倍。     

Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

A novel 4T-cell based duplication redundancy SRAM is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed SRAM structure exhibits high SEU hardening performance with a small cell size.     

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

A novel nine transistor (9T) CMOS SRAM cell design at 32 nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution at array-level, a novel write bitline balancing technique is proposed to reduce the leakage current. By optimizing its size and employing the proposed write circuit technique, 33% power dissipation saving is achieved in memory array operation compared with the conventional 6T SRAM based design. A new metric that comprehensively captures all of these figures of merit (and denoted to as SPR) is also proposed; under this metric, the proposed 9T SRAM cell is shown to be superior to all other cell configurations found in the technical literatures. The impact of the process variations on the cell design is investigated in detail. HSPICE simulation shows that the 9T SRAM cell demonstrates an excellent tolerance to process variations comparing with the conventional SRAM cells.     

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.     

High density and low leakage current based SRAM cell using 45 nm technology

This article is based on the observation of a Complementary Metal-Oxide Semiconductor (CMOS) five-transistor Static Random Access Memory (SRAM) cell (5T SRAM cell) for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. This 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 21.66% smaller than a conventional six-transistor SRAM cell using the same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The new 5T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45?nm technology.     

SRAM 6T存储单元电路的PSPICE辅助设计

首先从双稳态电路入手,分析了SRAM 6T单元电路的工作原理和设计要求。基于实际工艺下MOS晶体管的SPICE模型,给出了一组可行的设计参数。用PSPICE对设计出的6T存储单元进行了功能验证。     

三值钟控绝热静态随机存储器设计

通过对多值逻辑、绝热电路和三值SRAM结构的研究,提出一种新颖的三值钟控绝热静态随机存储器(SRAM)的设计方案。该方案利用NMOS管的自举效应,以绝热方式对SRAM的行列地址译码器、存储单元、敏感放大器等进行充放电,有效恢复储存在字线、位线、行列地址译码器等大开关电容上的电荷,实现三值信号的读出写入和能量回收。PSPICE模拟结果表明,所设计的三值钟控绝热SRAM具有正确的逻辑功能和低功耗特性,在相同的参数和输入信号情况下,与三值常规SRAM相比,节约功耗达68%。