采用一阶运放模型的开关电容电路分析

本文以非零主导极点模型代替开关电容(SC)电路中的非理想运放,得到连续条件下对SC网络拓扑无限制的频率响应式;对矩阵进行行列运算减少了电路变量,避免了复杂计算。这一分析方法已在IBM—PC微型机上实现。文中对二阶带通滤波电路的计算说明了运放有限增益带宽乘积对SC电路性能的影响,以及该分析方法的有效性。     

全差分超级自适应偏置跨导运算放大器

介绍了一种低电压、高效率的全差分自适应偏置跨导运算放大器。采用甲乙类的差分结构作为输入级,包含一个本地共模反馈结构(LCMFB),用以提供额外的电流自举,同时也提高其增益带宽积(GBW)和达到近乎理想的电流效率。采用TSMC 0.25μm标准工艺,实现全差分超级自适应运算放大器。为了比较,同时实现了传统的跨导运放和单端输出超级自适应运放。在10μA偏置电流和2 V工作电压下,与传统结构相比,超级自适应运放的转换速率提升了200倍,增益带宽积提高了4倍;而其全差分结构相对单端结构在几乎所有性能提升一倍的同时,还获得很好的共模抑制比和电源抑制比。     

一种动态开关电容运算放大器共模负反馈电路

本文主要介绍了一种应用于Cascode结构运放中的开关电容共模负反馈电路，它具有稳定性好、对运放频率特性影响小、不消耗额外功率等优点。对电路运用Hspice进行了模拟，并给出了模拟结果。     

一种低功耗可编程开关电容的分压电路

介绍了一种低功耗可编程分压电路,其静态功耗为零,输出电压不受工艺、温度影响,因此,在工程上具有广泛的应用前景。     

一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真.该电路采用了O.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真. 该电路采用了0.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

一种新的高性能开关电容排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

自适应偏置的低噪声放大器设计与实现

低噪声放大器作为射频接收系统中的关键器件,其噪声系数与线性度影响整个系统的性能。本文基于0.25μm GaAs pHEMT工艺设计了一款应用于DC～3 GHz的低噪声放大器。放大器采用耗尽型晶体管构成自适应偏置电路提升低噪声放大器线性度,通过源极高Q值电感优化噪声系数。该低噪声放大器芯片的测试结果表明,与传统偏置结构的放大器相比,随着输入功率的增大,该电路具有良好的栅电压补偿功能,噪声系数比传统结构减小0.5 dB以上,相同工作电流下输出功率1 dB压缩点提高11 dB,相同射频输出功率下直流功耗减小40%以上。     

偏置电压对射频/微波MEMS电容开关寿命的影响

理论分析了影响射频／微波MEMS电容开关寿命的因素：介质内的电场强度和可动薄膜对介质膜的冲击速度。用三种不同的偏置电压，对介质内电场强度和可动薄膜对介质膜的冲击速度进行了数值分析和比较。提出了在脉冲电压作用下，可得到可动薄膜对介质膜最小的冲击速度和介质内的最小电场强度，从而极大地提高MEMS电容开关运行的可靠性和寿命。实验验证了上述结论。     

一种新型跨导-电容滤波器自调谐电路

提出了一种基于开关电容技术的跨导一电容(Gm-C)滤波器自调谐电路.与基于压控振荡器(VCO)和压控滤波器(VCF)的传统调谐电路不同,该自调谐电路具有更高的精度和更低的功耗,且电路结构简单.设计了一个9阶椭圆函数低通滤波器,通过该调谐电路,实现了截止频率的精确可调.     

A Switched-Capacitor Adaptive Lattice Filter

Integration of an adaptive lattice filter in MOS-LSI technology is described. The architecture is designed to optimally exploit the advantages of analog and digital approaches. Switched-capacitor techniques are used for filtering and digital circuitry is used to perform the adaption. To test the concept, the analog circuitry was fabricated as an IC and operated with discrete digital circuitry. However, a complete monolithic implementation using this approach can be realized. The switched-capacitor metal-gate CMOS IC has die size of 18 500 mils/sup 2/ and power consumption of 108 mW.     

一种BiCMOS工艺的AB类自适应偏置输出级

介绍了一种采用 Bi CMOS工艺技术制造的具有较大的驱动能力、转换速率和较低的功耗的 AB类输出级。他是利用跨导线性原理实现自适应偏置的 AB类输出级。通过对这种结构的工作原理 ,结构特点的分析 ,仿真得出电阻负载为 2 kΩ ,电容负载为 1 0 0 p F时的最大上升、下降转换速率分别为 4 0 V/μs和 30 V/μs;在± 1 5 V的电源下 ,静态功耗小于 1 0 m W。     

一个0.9V低电压双端输出第二代电流传输器的设计

介绍一个0.9 V低电压双端输出第二代电流传输器(DOCCⅡ)的设计。输入级采用衬底驱动MOSFET有效地避免了阈值电压的限制;同时采用了局部正反馈技术提高了带宽增益,因此DOCCII获得了更好的电压跟随特性。该设计电路在标准0.18μm CMOS工艺下,采用Cadence Spectre和BSIM3v3模型对其进行了调试和仿真。仿真结果显示该DOCCII具有4.8MHz的带宽,同时具有比较高的线性度和很好的输入输出电阻。     

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

A Novel Dual-Rate Sampling Switched-Capacitor Configuration and Its Application

In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.     

一种用于开关电容电路的高性能运算放大器

设计了一种高性能BCMOS全差分运算放大器.该运放采用复用型折叠式共源共栅结构、开关电容共模反馈以及增益增强技术,在相同功耗和负载电容条件下,与传统CM0S增益增强型运算放大器相比,具有高单位增益带宽、高摆率及相位裕度改善的特点.在Cadence环境下,基于Jazz 0.35μm BiCMOS标准工艺模型,对电路进行Spectre仿真.在5 V电源电压下,驱动6pF 负载时,获得开环增益为115.3 dB、单位增益带宽为161.7 MHz、开环相位裕度为77.3°、摆率为327.0 V/μm、直流功耗(电流)为1.5 mA.     

一种基于衬底驱动技术的0.8 V高性能CMOS OTA

基于衬底驱动MOS技术,设计了一种0.8 V CMOS跨导运算放大器(OTA),在互补输入差分对的衬底端施加信号避开MOSFET阈值电压的限制以达到超低压应用,通过额外的共源放大器来提高OTA的增益.在±0.4 V的电源电压下,其直流开环增益为73.8 dB,单位增益带宽为16.4 MHz,相位裕度为53°,功耗为125.4 μW,输出电压范围为-0.337～0.370 V.     

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.     

A Passive Switched-Capacitor Finite-Impulse-Response Equalizer

A passive CMOS switched-capacitor finite-impulse-response equalizer is described. A sampling rate of 200 MS/s is achieved by six time-interleaved channels. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The 4-tap equalizer prototype is fully differential. At 200 MS/s, the equalizer dissipates 19.5 mW, which is virtually all consumed by clock drivers, and occupies an active area of 1.3 mm² in a 0.35 mum CMOS process