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1.
Mixed analog-digital signal processing aspects of a 5-V single-chip U-interface 2B1Q transceiver are discussed. Analog signal processing preconditions the signal by reducing jitter-induced echo and nonlinear echo components, and by maximizing the dynamic range utilization of the 13-b analog-to-digital (A/D) converter. The digital signal processor performs the high-pass filtering, precursor equalization, linear echo cancellation, far-end signal equalization, and timing recovery functions. The analog signal preconditioning technique allows the entire digital signal processing (DSP) section to be designed without a single dedicated multiplier. The U-interface transceiver has been realized in a 1.5-μm double-metal CMOS process, resulting in a circuit area of 77 mm2. Total power consumption is 300 mW. To comply with the ANSI-specified performance test procedures, a crosstalk noise generator and injection circuit were custom built along with a jitter generation system, all of which match the ANSI noise and jitter templates. Testing was performed over the 15 ANSI loops and countless other random configurations. Full compliance with the standard protocol and timing limits was achieved on all the loops  相似文献   

2.
A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply  相似文献   

3.
A multistandard rate adapter coprocessor chip, designed for use in ISDN terminal adapters and U-interface modems, is presented. It provides a compact, low-power protocol converter to connect asynchronous (up to 19200 b/s) and synchronous (up to 64 kb/s) data terminal equipment with any digital 64-kb/s network. The multistandard rate adapter chip was developed in a 2-μm CMOS technology using a hierarchical design methodology. The rate adapter is the cornerstone of a 144-kb/s U-interface modem and a major breakthrough for the next-generation multistandard terminal adapter  相似文献   

4.
A millimeter-wave IC dielectric resonator oscillator (DRO) is proposed. Equations that give the resonant frequency of the dielectric resonator DR in suspended stripline (SSL) are derived. A U-band voltage-controlled oscillator (VCO) with varactor tuning also has been developed. The Gunn diode and varactor used in both of the oscillators are commercially available packaged devices. Restrictions on the performance of the oscillators imposed by packaged and mounted networks and the self-characteristics of the solid-state devices have been analyzed. An electronic tuning range greater than 1000 MHz with an output power exceeding 15 dBm across the bandwidth in the 53-GHz region has been realized for the SSL VCO. An SSL DRO with an output power of more than 17 dBm and a mechanical tuning range of 1.5 GHz in the 54-GHz region has been achieved  相似文献   

5.
Optimum energy extraction from an electron-beam-pumped XeF(C A) laser is achieved with a five-component rare gas halide mixture. The characterization and modeling of laser action in such a gas mixture requires a knowledge of small-signal gain and absorption coefficients not only on the blue-green XeF(CA) transition, but also in the ultraviolet (UV) region for the competing XeF(BX) and KrF(BX ) transitions. The authors report gain measurements on the XeF(CA) transition and small-signal gain and absorption coefficients at or near both the XeF(BX ) (351 and 353 nm) and KrF(BX) (248 nm) transitions. A study of the gain for the UV and visible transitions as a function of Kr and Xe partial pressure is reported, and its impact on the XeF(CA) kinetics is discussed  相似文献   

6.
Hsu  C.-X. Wu  J.-L. 《Electronics letters》1988,24(6):315-316
An efficient algorithm is proposed which computes the coefficients of the higher order discrete Hartley transform (DHT) directly from the coefficients of lower-order DHTs. With this new development, the two-stage Walsh-Hadamard transform/discrete Hartley transform (WHT/DHT) is comparable to the existing fast algorithms. The same approach can also be used for the computation of DCT coefficients  相似文献   

7.
The effect of nonnormality on E{X} and R charts is reported. The effect of departure from normality can be examined by comparing the probabilities that E{X} and R lie outside their three-standard-deviation and two-standard-deviation control limits. Tukey's λ-family of symmetric distributions is used because it contains a wide spectrum of distributions with a variety of tail areas. The constants required to construct E{X} and R charts for the λ-family are computed. Control charts based on the assumption of normality give inaccurate results when the tails of the underlying distribution are thin or thick. The validity of the normality assumption is examined by using a numerical example  相似文献   

8.
Quarter-micron-gate-length high-electron-mobility transistors (HEMTs) have exhibited state-of-the-art low-noise performance at millimeter-wave frequencies, with minimum noise figures of 1.2 dB and 32 GHz and 1.8 dB at 60 GHz. At Ka-band, two-stage and three-stage HEMT low-noise amplifiers have demonstrated noise figures of 1.7 and 1.9 dB, respectively, with associated gains of 17.0 and 24.0 dB at 32 GHz. At V-band, two stage and three-stage HEMT amplifiers yielded noise figures of 3.2 and 3.6 dB, respectively, with associated gains of 12.7 and 20.0 dB and 60 GHz. The 1-dB-gain compression point of all the amplifiers is greater than +6 dBm. The results clearly show the potential of short-gate-length HEMTs for high-performance millimeter-wave receiver application  相似文献   

9.
Significant developments of the general optimum control theory presented in a previous paper by the authors (1988) are discussed for the specific case of multiphase matrix converters. Results hold, regardless of system configuration, input and output voltage waveforms, and loads. Applications to the most practical converter structures are illustrated, and implementation criteria of the optimum control method are derived. Simulated results confirm the flexibility and effectiveness of the approach  相似文献   

10.
The general concept of closest coset decoding (CCD) is presented, and a soft-decoding technique for block codes that is based on partitioning a code into a subcode and its cosets is described. The computational complexity of the CCD algorithm is significantly less than that required if a maximum-likelihood detector (MLD) is used. A set-partitioning procedure and details of the CCD algorithm for soft decoding of |u|u+v| codes are presented. Upper bounds on the bit-error-rate (BER) performance of the proposed algorithm are combined, and numerical results and computer simulation tests for the BER performance of second-order Reed-Muller codes of length 16 and 32 are presented. The algorithm is a suboptimum decoding scheme and, in the range of signal-to-noise-power-density ratios of interest, its BER performance is only a few tenths of a dB inferior to the performance of the MLD for the codes examined  相似文献   

11.
The design, fabrication, and evaluation of a W-band image-rejection downconverter based on pseudomorphic InGaAs-GaAs HEMT technology are presented. The image-rejection downconverter consists of a monolithic three-stage low-noise amplifier, a monolithic image-rejection mixer, and a hybrid IF 90° coupler with an IF amplifier. The three-stage amplifier has a measured noise figure of 3.5 dB, with an associated small signal gain of 21 dB at 94 GHz while the image-rejection mixer has a measured conversion loss of 11 dB with +10 dBm LO drive at 94.15 GHz. Measured results of the complete image-rejection downconverter including the hybrid IF 90° coupler and a 10 dB gain amplifier show a conversion gain of more than 18 dB and a noise figure of 4.6 dB at 94.45 GHz  相似文献   

12.
The design, fabrication, and evaluation of a fully integrated W-band monolithic downconverter based on InGaAs pseudomorphic HEMT technology are presented. The monolithic downconverter consists of a two-stage low-noise amplifier and a single-balanced mixer. The single-balanced mixer has been designed using the HEMT gate Schottky diodes inherent to the process. Measured results of the complete downconverter show conversion gain of 5.5 dB and a double-sideband noise figure of 6.7 dB at 94 GHz. Also presented is the downconverter performance characterized over the -35°C to +65°C temperature range. The downconverter design was a first pass success and has a high circuit yield  相似文献   

13.
The authors present the results of the construction and testing of three cryogenic low-noise GaAs FET amplifiers, based on a National Radio Astronomy Observatory design, to be used in a detector for the axion, a hypothetical particle. The amplifiers are centered on 1.1 GHz, and 2.4 GHz, have a gain of approximately 30 dB in bandwidths of 300 MHz, 225 MHz, and 310 MHz, and have minimum noise temperatures of 7.8 K, 8 K, and 15 K, respectively  相似文献   

14.
It is shown that m-sequences over GF(qm ) of length qnm-1 corresponding to primitive polynomials in GF[qm,x] of degree n can be generated from known m-sequences over GF(q) of length qnm-1 obtained from primitive polynomials in GF[q,x] of degree mn. A procedure for generating the m-sequences over GF(q2) from m-sequences over GF(q) was given which enables the generation of m-sequences over GF( p2n). In addition it was shown that all of the primitive polynomials in GF[q,m,x] can be obtained from a complete set of the primitive polynomials in GF[q ,x]  相似文献   

15.
A technique for the measurement of device derivatives d NV/dIN of arbitrary order N described. Measurement is accomplished by injecting a test current composed of the sum of N square waves into the rest device, and then multiplying the corresponding voltage change by the product of those same square waves, followed by low-pass filtering. The algorithm is implemented in real time using a mixture of analog and digital circuitry, and its application to semiconductor laser control in high-speed optical communications is described  相似文献   

16.
The authors discuss system and implementation aspects of a 144 kbit/s one-chip U-transceiver based on echo-cancellation techniques using the MMS43 line code and a Barker synchronization word for bit and frame timing, and including a 1-kb/s transparent channel for maintenance purposes. The LSI is realized by a 2-/spl mu/m CMOS, double-metal, double-poly technology shrinkable to a 1.5-/spl mu/m technology and packaged in a 28-pin DIL (dual in-line) package.  相似文献   

17.
18.
Channel codes where the redundancy is obtained not from parity symbols, but from expanding the channel signal-set, are addressed. They were initially proposed by G. Ungerboeck (1982) using a convolutional code. Here, a block coding approach is given. Rate m/(m+1) coded 2m+1-ary phase-shift keying (PSK) is considered. The expanded signal-set is given the structure of a finite field. The code is defined by a square nonsingular circulant generator matrix over the field. Binary data are mapped on a dataword, of the same length as the codewords, over an additive subgroup of the field. The codes using trellises are described, and then the Viterbi algorithm for decoding is applied. The asymptotic coding gain ranges from 1.8 to 6.0 dB for QPSK going from blocklength 3 to 12. For 8-PSK, the gain is from 0.7 to 3.0 dB with blocklength 4 to 8. With only four states in the trellis, codes of any length for QPSK and 8-PSK are constructed, each having an asymptotic coding gain of 3.0 dB. Simulation results are presented. It is found that the bit-error rate performance at moderate signal-to-noise ratios is sensitive to the number of nearest and next-nearest neighbors  相似文献   

19.
A novel method is presented for configuring an N× N passive star optical coupler and eliminating the excess loss problem associated with such couplers. A space-varying refractive index slab is introduced as a key design element for such a coupler. The wave mixing method is used to implement the coupler  相似文献   

20.
High-order, bidirectional, DC-20-GHz switch networks are discussed. Single-chip 1×2, 1×4, and 2×2 switch MMICs have been demonstrated. Multiple chips have been used to demonstrate 4×4 and 1×16 switches. The switches all use a combination of series and shunt passive FET switching elements. The 1×4 switch is made of a single stage of switching elements, rather than the usual two stages of 1×2 switches. The 2×2 switch is comprised of two stages of 1×2 switches. The multiple-chip 4×4 switch is made of four stages of 1×2 switches (using the 2×2 switch MMICs). Two stages of 1×4 switches are used to make the 1×16 switch  相似文献   

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