Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics

A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO₂ nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the I–V curve, a threshold voltage (V_T) of 2.2 V, a field-effect mobility on the order of 0.1 cm²/V s and an I_ON/I_OFF ratio of about 10⁴. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Thermal stability of lead-free CH3NH3SnxI3 systems (0.9 ≤ x ≤ 1.1) for photovoltaics

Methylammonium-tin-iodide (MASn_xI₃, 0.9 ≤ x ≤ 1.1) systems were prepared by precipitation process in aqueous solutions. The “as prepared” MASn_xI₃ systems exhibited a tetragonal crystalline phase (space group I4cm) with polyhedral crystallites (length 50–400 µm). The as prepared samples were annealed at T = 150 °C for t = 8 h under nitrogen and synthetic air. Under nitrogen, the CH₃NH₃Sn_xI₃ systems adopt nearly-cubic tetragonal structure (space group P4mm) with crystallites of 2–4 µm length whereas a degradation process with formation of non-crystalline phases occurred in air. The differential thermal analysis (DTA) profile in nitrogen revealed events at T = 247 °C, T = 297 °C (decomposition of CH₃NH₃Sn_xI₃ systems into methylamine (CH₃NH₂), hydroiodic acid (HI) and SnI₂), and in the range T = 342–373 °C (melting of SnI₂) respectively. The thermal profile in air showed endothermic events at T = 139 °C and T = 259 °C with additional events at onset temperatures of T = 337 °C and T = 423 °C respectively which correspond to the formation of Sn(IV)-O binds and to the decomposition of methylamine. Static thermogravimetry analysis (TG), performed at T = 85 °C and T = 150 °C for t = 2 h, revealed a linear weight loss as a function of the time. The optical absorption spectra displayed absorbance edges in near infrared range, at 1107.0 nm (x = 0.9), 1098.6 nm (x = 1.0) and 1073.2 nm (x = 1.1) respectively.     

Overdamped NbN junctions with NbNx barriers formed by plasma nitridation

We have fabricated NbN Josephson junctions with NbN_x barriers formed by plasma nitridation on the surface of the base superconductive NbN layer. Both nonhysteretic junctions (overdamped junctions) and small-hysteretic ones have been obtained at 4.2 K by changing plasma nitridation conditions. An overdamped junction showed a product of the critical current I_c and junction resistance R_n (an I_cR_n product) of 0.95 mV at 4.2 K and the I_c exponentially decreased with increasing temperature. On the other hand, a small-hysteretic junction showed Superconductor-Insulator-Superconductor (SIS)-like characteristics in the temperature dependence of I_c and its current–voltage characteristics changed to nonhysteretic ones at the temperature more than 8 K. The I_cR_n product for the junction was 0.91 mV at 8.2 K.     

TiSiOx gate dielectrics produced by reactive sputtering for high performance InGaZnO thin film transistors

High dielectric constant TiSiOx thin films are produced by reactive sputtering under different oxygen partial pressure ratio (P_O2) from 15% to 30%. All the TiSiOx films show an excellent transmittance value of almost 95%. The TiSiOx film has a low leakage current density by optimizing oxygen partial pressure, and the leakage current density of TiSiOx film under P_O2 of 20% is 4.88×10⁻⁷ A/cm² at electrical field strength of 2 MV/cm. Meanwhile, their associated InGaZnO thin-film transistors (IGZO-TFTs) with different P_O2 TiSiOx thin films as gate insulators are fabricated. IGZO-TFTs under P_O2 of 20% shows an optimized electrical performance, and the threshold voltage, sub-threshold swing, field effect mobility and I_on/I_off ratio of this device are 2.22 V, 0.33 V/decade, 29.3 cm²/V s and 5.03×10⁷, respectively. Moreover, the density of states (DOS) is calculated by temperature-dependent field-effect measurement. The enhancements of electrical performance and temperature stability are attributed to better active/insulator interface and smaller DOS.     

Benzopyrazine-fused tetracene derivatives: Thin-film formation at the crystalline mesophase for solution-processed hole transporting devices

Benzopyrazine-fused tetracene (TBPy) and its disulfide (TBPyS) bearing alkoxy groups (OCH₃, OC₈H₁₇) were designed and synthesized to obtain π-expanded tetracene derivatives. These derivatives are featured with long-wavelength light absorption property (λ_onset: up to 820 nm), photooxidative stability (half-lives (τ_1/2): 11 times longer than tetracene), and solubility for solution process. The methoxy compounds (TBPy-C1 and TBPyS-C1) were used for single-crystal X-ray crystallographic analysis and single-crystal organic field-effect transistor (OFET) devices showing relationship between packing structures and hole mobilities. The octyloxy compounds (TBPy-C8 and TBPyS-C8) were investigated on solution-processed thin-film formation and hole transport property in thin-film OFET devices. Crystalline mesophase of TBPy-C8 and TBPyS-C8 was characterized by differential scanning calorimetry analysis showing endothermic peaks at 98 and 198 °C on its second heating process and exothermic peaks at 177 and 76 °C on its second cooling process for TBPyS-C8, and played crucial roles in thin-films formation. Hole mobility of 1.7 × 10^?2 cm²/V s (with V_th = ?30 V and I_ON/I_OFF = 10⁴) was obtained for the thin-film OFET device of TBPyS-C8.     

Biaxially aligned YBCO film tapes fabricated by all pulsed laser deposition

Biaxially aligned yttria-stabilized zirconia (YSZ) films on Ni-based alloy substrates were realized with high deposition rate of 0.5 μm min⁻¹ by the inclined substrate deposition (ISD) technique without ion beam assistance. The microstructure of YSZ was examined to study the growth mechanism of biaxial alignment by ISD. Columnar structures toward the plasma plume suggested a self-shadowing effect in the ISD process. To raise I_c values, YBCO thickness was increased up to 5 μm. Thick YBCO films with high J_c values were realized on the ISD-grown YSZ. Long YBCO tapes with biaxial alignment were successfully fabricated using continuous pulsed laser deposition and a high I_c value of 37.0 A (77.3 K, 0 T) at a 75 cm voltage tap spacing was achieved.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Impact of source-to-drain tunnelling on the scalability of arbitrary oriented alternative channel material nMOSFETs

In this work, the scalability of alternative channel material double gate nano nMOSFETs has been investigated by the mean of semi-analytical models of I_on/I_off currents, accounting for quantum capacitance degradation, short channel effects, band-to-band and source-to-drain tunnelling in arbitrary substrate and channel direction.Contrary to most of the previous study neglecting source-to-drain tunnelling, it has been found that for devices with physical gate length below 13 nm (as required in the 22 and 16 nm nodes), this mechanism significantly penalises the I_on/I_off trade off of small effective masses channel materials like Ge or GaAs, much more than in the case of Si and biaxially strained Si (s-Si). In addition, only strained Si-MOSFETs has been found to meet the performance expectation of the International Technology Roadmap of Semiconductor for the 22 nm and 16 nm technological nodes.     

Non-functionalized soluble diketopyrrolopyrrole: Simplest p-channel core for organic field-effect transistors

We report the synthesis, characterization and behavior in field-effect transistors of non-functionalized soluble diketopyrrolopyrrole (DPP) core with only a solubilizing alkyl chain (i.e. –C₁₆H₃₃ or –C₁₈H₃₇) as the simplest p-channel semiconductor. The characteristics were evaluated by UV–vis and fluorescence spectroscopy, X-ray diffraction, cyclic voltammetry (CV), thermal analysis, atomic force microscopy (AFM) and density functional theory (DFT) calculation. For top-contact field-effect transistors, two types of active layers were prepared either by a solution process (as a 1D-microwire) or thermal vacuum deposition (as a thin-film) on a cross-linked poly(4-vinylphenol) gate dielectric. All the devices showed typical p-channel behavior with dominant hole transports. The device made with 1D-microwiress of DPP-R18 showed field-effect mobility in the saturation region of 1.42 × 10^?2 cm²/V s with I_ON/I_OFF of 1.82 × 10³. These findings suggest that the non-functionalized soluble DPP core itself without any further functionalization could also be used as a p-channel semiconductor for low-cost organic electronic devices.     

Defects annealing in 4H–SiC epitaxial layer probed by low temperature photoluminescence

The thermal evolution of defects induced in 4H–SiC by multiple implantation of C ions was investigated by Low Temperature Photoluminescence in the temperature range 450–1000 K. The photoluminescence spectra show sharp luminescent lines (alphabet lines) in the wavelength range 426–440 nm upon irradiation and thermal treatment at 450 K induces the appearance of a new line at 427 nm (D_I centre). The trend shown by the luminescence lines as a function of the temperature is quite complex. The alphabet lines intensity increases up to 850 K, whereas at higher temperature decreases with an activation energy of 2.0 eV, suggesting that the defect, responsible for these lines, is the Si-vacancy. The luminescence yield of D_I centre is always increasing as a function of the temperature, with a higher slope from 750 K, suggesting a correlation to the reconfiguration and to the annealing of point defects.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

Characterization of AZO/p-Si heterojunction prepared by DC magnetron sputtering

Al-doped ZnO (AZO) film was deposited by direct-current (DC) magnetron sputtering on p-Si (1 0 0) wafer to fabricate Al-doped n-ZnO/p-Si heterojunctions. The microstructural, optical and electrical properties of the AZO film were characterized by XRD, SEM; UV–vis spectrophotometer; four-point probe and Hall effect measurement, respectively. Results show that the AZO film is of good quality. The electrical junction properties were investigated by I–V measurement, which reveals that the heterojunction shows rectifying behavior under a dark condition. The ideality factor and the saturation current of this diode are 20.1 and 1.19×10⁻⁴ A, respectively. The value of I_F/I_R (I_F and I_R stand for forward and reverse current, respectively) at 5 V is found to be as high as 19.7. It shows fairly good rectifying behavior, indicating formation of a diode between AZO and p-Si. High photocurrent is obtained under a reverse bias when the crystalline quality of AZO film is good enough to transmit light into p-Si.     

The effect of annealing temperature on the electronic parameters and carrier transport mechanism of Pt/n-type Ge Schottky diode

The Pt nano-film Schottky diodes on Ge substrate have been fabricated to investigate the effect of annealing temperature on the characteristics of the device. The germanide phase between Pt nano-films and Ge substrate changed and generated interface layer PtGe at 573 K and 673 K, Pt₂Ge₃ at 773 K. The current–voltage(I - V) characteristics of Pt/n-Ge Schottky diodes were measured in the temperature range of 183–303 K. Evaluation of the I - V data has revealed an increase of zero-bias barrier height Φ_B0 but the decrease of ideality factor n with the increase in temperature. Such behaviors have been successfully modeled on the basis of the thermionic emission mechanism by assuming the presence of Gaussian distributions. The variation of electronic transport properties of these Schottky diodes has been inferred to be attributed to combined effects of interfacial reaction and phase transformation during the annealing process. Therefore, the control of Schottky barrier height at metal/Ge interface is important to realize high performance Ge-based CMOS devices.     

Evaluation of lateral barrier height of inhomogeneous photolithography-fabricated Au/n-GaAs Schottky barrier diodes from 80 K to 320 K

In order to evaluate current conduction mechanism in the Au/n-GaAs Schottky barrier diode (SBD) some electrical parameters such as the zero-bias barrier height (BH) Φ_bo(I–V) and ideality factor (n) were obtained from the forward bias current–voltage (I–V) characteristics in wide temperature range of 80–320 K by steps of 10 K. By using the thermionic emission (TE) theory, the Φ_bo(I–V) and n were found to depend strongly on temperature, and the n decreases with increasing temperature while the Φ_bo(I–V) increases. The values of Φ_bo and n ranged from 0.600 eV and 1.51(80 K) to 0.816 eV and 1.087 (320 K), respectively. Such behavior of Φ_bo and n is attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution (GD) of BHs at Au/n-GaAs interface. In the calculations, the electrical parameters of the experimental forward bias I–V characteristics of the Au/n-GaAs SBD with the homogeneity in the 80–320 K range have been explained by means of the TE, considering GD of BH with linear bias dependence.     

High-resolution transmission electron microscopy study on bipolar resistive switching behavior in TiO2 thin films

We fabricated TiO₂ thin films the by sol–gel process. Successful I–V curves can be obtained in the Cu/TiO₂/ATO structure device in which TiO₂ thin film was calcined at 300 °C. The bipolar resistive switching behavior was observed and the ratio of R_off/R_on can be increased to 10⁴. The switching voltage changes from 4.8 to 3.5 V when the current compliance drops from 10 to 0.1 mA. We also investigated the microstructure by HRTEM technology.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

A novel method to improve cell endurance window in source-side injection split gate flash memory

To enhance cell endurance window of a split gate flash memory, we used a ramp pulse with long rising time to replace the conventional square pulse for programming. The change is based on the study of the electric field at electron injection point (E_G) related to programming time. Statistic measurements on various samples including different technologies, cell locations (even or odd) and rise times were done. The results confirm that the read currents shift under erase state (ΔI_r1) could be improved significantly with an acceptable programming speed by the proposed method.For example, as increasing the rising time from 0.1 μs to 20 μs for the conventional square pulse and the ramp pulse respectively, after 1 M cycling the ΔI_r1 is reduced from 64.8% to 36.2% with an acceptable minimum programming time of 12.5 μs.     

Channel width effect for organic thin film transistors using TIPS-pentacene employed as a dopant of poly-triarylamine

The effects of the physical channel width on the characteristics of organic thin film transistors (OTFTs), made with 6,13-bis(triisopropyl-silylethynyl)-pentacene (TIPS-pentacene) embedded into poly-triarylamine (PTAA, hole conductor within an active channel), have been examined in this paper. The devices are estimated by measuring the drain-source current (I_DS) for different contact metals such as Au and Ag, at fixed gate and drain voltages. The results show that the threshold voltage (V_T) and I_DS increase with increasing channel width. Furthermore, it has been observed that the field effect mobility is dependent on V_T, which is influenced by the channel width. The OTFTs, produced using Au and Ag contacts, exhibited the highest values of mobility in the saturation regime, namely 5.44 × 10^?2 and 1.33 × 10^?2 cm²/Vs, respectively.     

The influence of junction depth on short channel effects in vertical sidewall MOSFETs

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junction depths in vertical MOSFETs, it is necessary to look separately at the electrostatic influence of each junction. In order to suppress short channel effects better, we explore the formation of a shallow drain junction. This is realized by a self-aligned oxide region, or junction stop (JS) which is formed at the pillar top and acts as a diffusion barrier for shallow junction formation. The benefits of using a JS structure in vertical MOSFETs are demonstrated by simulations which show clearly the effect of asymmetric junctions on SCEs and bulk punch-through. A critical point is identified, where control of SCEs by junction depth is lost and this leads to appropriate junction design in JS vertical sidewall MOSFETs. For a 70 nm channel length the JS structure improves charge sharing by 54 mV and DIBL by 46 mV. For body dopings of 5.0 × 10¹⁷ cm^?3 and 6.0 × 10¹⁷ cm^?3 the JS gives improvements in I_off of 58.7% and 37.8%, respectively, for a given I_on. The inclusion of a retrograde channel gives a further increase in I_on of 586 μA/μm for a body doping of 4.0 × 10¹⁸ cm^?3.