2D TMD Channel Transistors with ZnO Nanowire Gate for Extended Nonvolatile Memory Applications

2D transition metal dichalcogenides (TMDs) have been extensively studied due to their excellent physical properties. Mixed dimensional devices including 2D materials have also been studied, motivated by the possibility of any synergy effect from unique structures. However, only few such studies have been conducted. Here, semiconducting 1D ZnO nanowires are used as thin gate material to support 2D TMD field effect transistors (FETs) and 2D stack‐based interface trap nonvolatile memory. For the trap memory, deep level electron traps formed at the first MoS₂/second MoS₂ stack interface are exploited, since the first MoS₂ is treated in an atomic layer deposition chamber for a short while. On the one hand, a complementary inverter type memory device can also be achieved using a long single ZnO wire as a common gate to simultaneously support both n‐ and p‐channel TMD FETs. In addition, it is found that the semiconducting ZnO nanowire itself operates as an n‐type channel when the TMD materials can become a top‐gate to charge the ZnO channel. It means that 2D (bottom gated) and 1D channel (top gated) FETs are respectively operational in a single device structure. The 1D–2D mixed devices seem deserving broad attention in both aspects of novelty and functionality.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

Quality factor and frequency bandwidth of 2D self-inductors in 3D integration stacks

Effects due to 3D level stack on high frequency (HF) properties of 2D self-inductors integrated in the back end of line (BEOL) are investigated. Different stacking processes as Back to Face and Face to Face using a molecular SiO₂ bonding or a copper direct bonding are studied in order to determine silicon substrate stack influence on quality factor and frequency bandwidth of 2D self-inductors. Face to Face process with a molecular SiO₂ bonding allows improvements of self-inductor performances, better than Back to Face process with a molecular SiO₂ bonding and better than Face to Face process using a copper direct bonding.     

An efficient two-dimensional model for CMOS latchup analysis

A general structure-oriented model has been specially designed to estimate the substrate spreading resistance of a parasitic SCR latchup path in a CMOS structure, which can handle CMOS structures with normal and reverse layouts in the substrate, with top and back substrate contacts, and with an epitaxial layer in the substrate. The simplified 2D numerical analysis based on solving the Laplace equation has been carried out and used to quantitatively evaluate the substrate spreading resistance of a parasitic SCR latchup path. Based on the calculated substrate spreading and well resistances, the holding voltage and holding current as well as the triggering current have been calculated and compared with the experimental measurements. Moreover, the predicted holding voltage value is shown to be nearly identical to that obtained using the full 2D numerical analysis for a specified CMOS latchup path. In addition, the developed model has been thoroughly applied to evaluate a variety of the CMOS structures and close correlations between the predicted results and the reported latchup experiments are quite encouraging. Furthermore, a latchup-free CMOS structure predicted by the developed model has been shown to be consistent with some experimentally verified latchup-free structures published in the literature.     

Controlled Folding of 2D Au–Polymer Brush Composites into 3D Microstructures

Microscale, quasi‐2D Au–polymer brush composite objects are fabricated by a versatile, controllable process based on microcontact printing followed by brush growth and etching of the substrate. These objects fold into 3D microstructures in response to a stimulus: crosslinked poly(glycidyl methacrylate) (PGMA) brushes fold on immersion in MeOH, and poly(methacryloxyethyl trimethylammonium chloride) (PMETAC) brushes fold on addition of salt. Microcages and microcontainers are fabricated. A multistep microcontact printing process is also used to create sheets of Au–PGMA bilayer lines linked by a PGMA film, which fold into cylindrical tubes. The bending of these objects can be predicted, and hence predefined during the synthesis process by controlling the parameters of the gold layer, and of the polymer brush.     

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85?%, a relative yield improvement of 118.79?% is obtained with two redundant layers, while this is 14.03?% only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68?% when using layer redundancy and only with 12.48?% when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Surface charging suppression using PEDOT/PSS in the fabrication of three dimensional structures on a quartz substrate

Pattern writing on insulating materials (e.g. quartz) using electron beam lithography (EBL) is a challenging task and it is even more difficult when the pattern is three dimensional (3D). Surface charging trapped on insulating substrates may deflect the electron beam during electron beam pattern writing causing undesired effects.In this work, the surface charging has been suppressed by top coating with water soluble conductive polymer layer using poly (3,4-Etylenedioxythiophene)/poly(styrenesulfonate) (PEDOT/PSS). The 3D masking profiles are created on a negative tone photoresist (Microresist, ma-N2403) using Raith150 EBL tool with variable dose controlled beam exposure. The 3D patterns have been transferred onto the quartz substrate by single step reactive ion etching (RIE) with suitable resist to substrate selectivity.We have demonstrated the fabrication of 3D geometrical shapes such as pyramids, hemispheres, and cones with dimensions down to 300 nm using this technique without any surface charging effects.     

New technology on tri-level resist doped with dye for submicron photolithographic process

New tri-level resist structures for photolithography have been developed for volume VLSI production with submicron geometries. Organosilica film is used as an intermediate layer. This film can be formed by a spin-coating process and has a sufficient tolerance for O₂ reactive sputter etching. Both standing waves in top layer and linewidth variation on substrate steps are prevented by incorporating absorption dye into an organosilica intermediate layer. The complex refractive index for organosilica with absorption dye was measured, and the absorbed energy profile inside the top layer resist was calculated. Excellent properties in the present technology are proved by the experimental and calculated results.     

A novel sacrificial gate stack process for suppression of boronpenetration in p-MOSFET with shallow BF2-implantedsource/drain extension

A novel process flow employing a sacrificial tetraethyl orthosilicate/polycrystalline silicon (TEOS/poly-Si) gate stack is proposed for fabricating fluorine-enhanced-boron-penetration-free p-channel metal oxide semiconductor field effect transistors (p-MOSFET's) with shallow BF₂-implanted source/drain (S/D) extension. With the presence of the sacrificial TEOS/poly-Si gate stack as the mask during the shallow BF₂ implant, the incorporated fluorine atoms are trapped in the sacrificial TEOS top layer and can be subsequently removed. The new process thus offers a unique opportunity of achieving an ultra shallow S/D extension characteristic of the BF₂ shallow implant, while not suffering from any fluorine-enhanced boron penetration normally accompanying the BF₂ implant. Excellent transistor performance with improved gate oxide integrity has been successfully demonstrated on p-MOSFET's fabricated with the new process flow     

On the Principles of Printing Sub‐micrometer 3D Structures from Dielectric‐Liquid‐Based Colloids

Dielectrophoresis‐assisted (DEP) on‐demand printing of dielectric‐liquid‐based colloidal gold under room conditions is demonstrated and employed to print 2D and 3D structures with sub‐micrometer feature sizes. The focus of the work is primarily on explaining the physics of the printing process, based on the formation of a controlled sequence of sub‐micrometer drops. The physics of 3D structure formation on the substrate is explained through the visualization and analysis of various time‐scales relevant to the printing process and the pinning of the contact line of the printed colloids. A parametric variation of the related variables, namely the applied voltage and the pulse length, is used to investigate the morphology and topography of a host of basic, printable 2D and 3D features. It is established that it is possible to obtain uniform particle deposits in 2D by filling up an initial coffee‐ring‐type non‐uniform deposit with a series of subsequently formed drops, all obtained during a single electric pulse. Finally, on‐demand production of multilayered, sub‐micrometer gold tracks is demonstrated, where the annealed tracks exhibit exceptionally low electrical resistivity for their sizes, only two times higher than that of bulk gold.     

IMC Growth at the Interface of Sn–2.0Ag–2.5Zn Solder Joints with Cu,Ni, and Ni–W Substrates

Growth of intermetallic compounds (IMC) at the interface of Sn–2.0Ag–2.5Zn solder joints with Cu, Ni, and Ni–W substrates have been investigated. For the Cu substrate, a Cu₅Zn₈ IMC layer with Ag₃Sn particles on top was observed at the interface; this acted as a barrier layer preventing further growth of Cu–Sn IMC. For the Ni substrate, a thin Ni₃Sn₄ film was observed between the solder and the Ni layer; the thickness of the film increased slowly and steadily with aging. For the Ni–W substrate, a thin Ni₃Sn₄ film was observed between the solder and Ni–W layer. During the aging process a thin layer of the Ni–W substrate was transformed into a bright layer, and the thickness of bright layer increased with aging.     

3D monolithic integration: Technological challenges and electrical results

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650 °C). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.     

Chemiresistive sensor fabricated by the sequential ink-jet printing deposition of a gold nanoparticle and polymer layer

A technique for the fabrication of chemiresistive sensors using ink-jet printing is reported. Gold nanoparticles stabilised in water were ink-jet printed on gold interdigitated electrodes patterned on an oxidized silicon wafer. As a first step the influence of substrate functionalization, electrode spacing, and nanoparticle density were investigated by electrical measurements and microscopy imaging. Finally a second layer of PHEMA polymer was printed on top of the gold nanoparticle films. The device was exposed to vapours of humidity and ethanol and the obtained results are presented.     

A nanoanalytical investigation of the Ga2O3/GaGdO dielectric gate stack for InGaAs based MOSFET devices

In this paper, a subnanometer characterization of the Ga₂O₃/GdGaO dielectric gate stack grown on top of InGaAs lattice matched to n⁺ InP substrate is presented. The paper shows the analysis of two samples grown using different substrate temperature. This clearly affects the electrical characteristics as well as the photoluminescence properties. The paper also describes how the growth conditions of oxide stack affect the elemental distribution across the interface region.     

基于硅基堆叠SIP技术的超宽带T/R组件

传统的超宽带T/R组件采用的是两维砖块式结构,体积和重量已不适应目前小型化、低剖面、易共形的相控阵天线要求。文中提出的基于硅基堆叠系统级封装(SIP)技术,将四通道的射频芯片高度集成在硅基介质基板上,将多层介质基板厚金压合,实现多层堆叠的三维封装。通过采用芯片多功能集成技术和超宽带射频信号的垂直互连技术,设计出三维堆叠的四通道超宽带T/R组件。T/R组件带宽为6 GHz～18 GHz,单通道的发射功率优于23 dBm,接收增益优于20 dB,可实现6位数控衰减及6位数控移相,尺寸仅有13.0 mm×13.0 mm×3.4 mm。该技术可以实现多通道超宽带T/R组件的SIP封装,有利于工程应用。     

用于后端工艺中铜/低k材料金属去除的实验数值研究

1 Introduction The consumer electronics market demands high-er speeds and more functionality of ICs. Speed and functionality of an IC are related to the amount of cir- cuitry (such as transistors), which is packed on eachchip. Therefore, the dimensions of the transistors need to be reduced. The interconnect structure, which con- nects the transistors, must become smaller too to com- ply with the small dimensions of the transistors. In or- der to reduce undesirable effects[1], which follow fr…     

A new SOI high voltage device based on E-SIMOX substrate

A new NI (n+ charge islands) high voltage device structure based on E-SIMOX (epitaxy-the separation by implantation of oxygen) substrate is proposed. It is characterized by equidistant high concentration n+-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field (Ev) are located in the spacing of two neighboring n+-regions on the interface by the force from lateral electric field (EL) and the compositive operation of Coulomb's forces with the ionized donors in the undepleted n+-regions. This effectively enhances the electric field of dielectric buried layer (EI) and increases breakdown voltage (Vb). An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology (E-SIMOX).