Flip the tip: an automated,high quality,cost-effective patch clamp screen

The race for creating an automated patch clamp has begun. Here, we present a novel technology to produce true gigaseals and whole cell preparations at a high rate. Suspended cells are flushed toward the tip of glass micropipettes. Seal, whole-cell break-in, and pipette/liquid handling are fully automated. Extremely stable seals and access resistance guarantee high recording quality. Data obtained from different cell types sealed inside pipettes show long-term stability, voltage clamp and seal quality, as well as block by compounds in the pM range. A flexible array of independent electrode positions minimizes consumables consumption at maximal throughput. Pulled micropipettes guarantee a proven gigaseal substrate with ultra clean and smooth surface at low cost.     

Biophysical properties of Kv3.1 channels in SH-SY5Y human neuroblastoma cells

Biophysical properties of delayed rectifier K channels in the human neuroblastoma SH-SY5Y were established using patch clamp recordings. The whole cell K+ conductance activated at membrane potentials positive to -20 mV. The midpoint of current activation was 9.6 +/- 5.1 mV, the equivalent charge was 3.7 +/-.6. Whole-cell currents inactivated slightly with time constants of 700 ms and 5 s. The K+ currents were sensitive to micromolar concentrations of TEA and 4-aminopyridine. RT-PCR experiments amplified a cDNA fragment specific for human Kv3.1 channels. Activation gating parameters in outside-out patches were shifted by approximately 14 mV in the hyperpolarizing direction.     

亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.     

亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.     

Identification of hidden Markov models for ion channel currents. I.Colored background noise

Signal processing based on hidden Markov models (HMM's) has been applied recently to the characterization of single ion channel currents as recorded with the patch clamp technique from living cells. The estimation of HMM parameters using the traditional forward-backward and Baum-Welch algorithms can be performed at signal-to-noise ratios (SNR's) that are too low for conventional analysis; however, the application of these algorithms relies on the assumption that the background noise is white. In this paper, the observed single channel current is modeled as a vector hidden Markov process. An extension of the forward-backward and Baum-Welch algorithms is described to model ion channel kinetics under conditions of colored noise like that seen in patch clamp recordings. Using simulated data, we demonstrate that the traditional algorithms result in biased estimates and that the vector HMM approach provides unbiased estimates of the parameters of the underlying hidden Markov scheme     

Characterization of a MEMS BioChip for planar patch-clamp recording

We describe a planar MEMS silicon structure to record ion channel currents in biological cells. The conventional method of performing an electrophysiological experiment, `patch-clamping', employs a glass micropipette. The micropipette tip is a source of thermal noise because of its inherent, tapered, conical structure, giving rise to a large pipette resistance. This pipette resistance, when coupled with the biological cell capacitance, limits the available bandwidth of single ion channel recording. In this work, we propose a current transport model to characterize the series resistance and capacitance of a planar pipette fabricated on a silicon BioChip. Our model provides a deeper insight into how currents injected into a micropore are quantitatively partitioned into the individual ion transports, and goes beyond just describing the solute and solvent kinetics inside pores of microscale dimensions. The device topology and fabrication sequence of the planar patch-clamp setup are also discussed. The theoretical predictions by the model are in close agreement with the experimental results.     

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。     

The action potential clamp as a test of space-clamp effectiveness--the Lettvin analog axon

For a Lettvin analog axon, in which spurious currents due to inadequate space clamp are absent, the action potential clamp technique accurately reproduces the original stimulating current. The action potential generated for the first phase of the experiment is stored digitally. When this action potential waveform is used for the voltage clamp phase of the experiment, digital noise in the resultant current record is a factor of ten smaller than that of the reproduced current record. The requirement of rapid transition between the two experimental components for such experiments with squid giant axon is examined.     

Micromachined pipette arrays

In this paper, the design and characterization of batch fabricated metallic micromachined pipette arrays is described. The process used to fabricate the micromachined pipette arrays (MPA) includes p+ etch-stop membrane technology, anisotropic etching of silicon in potassium hydroxide, sacrificial thick photoresist micromolding technology, and electrodeposition. Arrays of one to ten pipettes have been fabricated using nickel as the structural material and palladium as the biocompatible coating of inside walls. The inner dimensions of the individual pipettes fabricated to date range from 30 microns to 1.5 mm in width, 0.5 mm to several cm in length, and 5-50 microns in thickness. The center-to-center spacing of these pipettes varies from 100 microns to several centimeters. The MPA have a number of advantages when compared to the current micropipette technology, including the ability to transfer precise volumes of samples in the submicroliter range; the ability to manipulate samples, reagents, or buffers in a highly-parallel fashion by operating hundreds of individual pipettes simultaneously; and the compatibility with the submilimeter center-to-center dimensions of the microscale biochemical analysis systems. The application of the MPA to high lane density slab gel electrophoresis is explored. Sample wells are formed in agarose gels by using micromachined combs (solid MPA) at center-to-center spacing ranging from 250 microns to 1.9 mm. The samples are loaded using the MPA. The results of the micro-gel separations compare favorably with the standard mini-gel separations and show a twofold increase in the number of theoretical plates as well as a sixfold increase in lane density.     

膜片钳放大器的低噪声设计

本文论述用于测量细胞膜离子通道电流的放大器的电路方案.因被测电流在1pA到nA级的范围内,而输出电压要求达到计算机便于处理的数值.故需采用多级放大电路.被测电流属极微弱的信号,噪声问题是设计中的关键.对于多级放大器来说,前置放大级(探头电路)的低噪声设计至关重要.文中分析放大电路中的主要元、器件的背景噪声,用噪声电流和噪声电压的功率密度谱(PDS)S_I(f)和S_v(f)来表征其特性.给出了所设计的PC-Ⅱ型膜片钳放大器的主要性能参数和记录的电流波形.     

1/f noise and specific detectivity of HgCdTe photodiodes passivatedwith ZnS-CdS films

1/f noise in HgCdTe photodiodes has been measured as a function of temperature, diode bias, and dark current. The dependence of 1/f noise on dark current was measured over a wide temperature range. At low temperatures, where surface generation and leakage current were predominant, a linear relationship between 1/f noise and dark current was observed. At higher temperatures, where diffusion current is predominant, the correlation no longer holds. The temperature dependence of 1/f noise was also determined. The temperature dependence of the 1/f noise was found to be the same as that for the surface generation and leakage currents. All the data obtained in these experiments could be fit with theoretical predictions by a simple relationship between 1/f noise and dark current. The 1/f noise in the HgCdTe photodiode varies with diode bias, temperature, and dark current only through the dependence of the surface current on these devices. The maximum specific detectivity (D*) value and the maximum signal-to noise ratio are approximately 3.51×10¹⁰ cm·Hz^1/2/W and 5096 at 50 mV reverse bias, respectively     

Mechanoelectrical feedback in cardiac myocytes fromstretch-activated ion channels

Stretch-activated ion channels (SACS) in cardiac myocytes from neonatal rats were studied in cell-attached patches. Stretch of membrane patches by suction in the recording pipette caused the triggering of action potentials that were recorded as action currents (ACs). The significance of a temporal correlation between SAC open probability and ACs was tested using the Kolmogorov-Smirnov and Poisson distributions. It was shown that the 50-ms epoch immediately preceding the action current has unique kinetics and represented a peak in SAC open probability (p<0.001). Thus it appears that current from a small number of SAC's injects sufficient charge (0.2 pC during 50 ms) to trigger action potentials in myocytes. These data strengthen the hypothesis that passive mechanical stretch of myocardium can be arrhythmogenic     

InGaAsP channel HFET's on InP for OEIC applications

A model for the calculation of the input noise of a high impedance photoreceiver is proposed, taking into account the contributions of low-frequency characteristics of the FET. Simulations based on this approach show that excess gate leakage current and low-frequency excess noise, usually observed in InGaAs channel FET's, strongly penalize the photoreceiver sensitivity for low to medium data rates. New InGaAsP channel HFET's have been developed and fabricated to solve those problems, dc measurements on 1×100 μm² gate HFET's show good I_ds-V_ds characteristics with associated gate leakage currents lower than 200 nA. Promising ft of 18 GHz and f _max of 40 GHz have been recorded on 0.5×200 μm² gate transistors. Low-frequency gate and channel noise measurements demonstrate the suitability of InGaAsP channel HFET structure and technology for low noise applications. A hybrid pin-HFET high impedance photoreceiver has been assembled with a 1×150 μm ² gate transistor. A very close agreement is found between photoreceiver input noise predicted by our model and experimental results. Record sensitivities of 34.8 dBm at 622 Mbit/s and -28.7 dBm at 2.5 Gbit/s are inferred from noise measurements, confirming the strong potential of InGaAsP channel HFET's for the fabrication of high sensitivity photoreceivers operating at moderate data rates     

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

Leakage current is of great concern for designs in nanometer technologies. In 90- and 65-nm technologies, subthreshold leakage current dominates total leakage current. For a typical ASIC circuit running at several hundred megahertz frequencies, the subthreshold leakage power can be as high as 60% of total power. An important method for minimizing power in ASIC libraries is reducing leakage current. In this article, a complete automated leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed. Optimization results show that there is ~30% leakage current reduction with a few percent active area and delay increase. There is increase in dynamic power, but the net total power reduction is significant. A uniform increase of 10% in gate length results in ~35% leakage reduction at the cost of ~12% delay degradation. The total cell area changes are minimal in both cases. The optimization flow begins with SPICE net lists from an existing library, optimizes leakage currents subject to performance metrics and active area increase constraints, and finishes with new layout generation and characterization. Investigations indicate that the leakage optimization has little impact on cell noise margin and layout parasitic modifications do not affect optimization results. The efficient automatic layout-to-layout cell leakage optimization flow is most suitable for leakage minimization and library migration for 90- and 65-nm ASIC libraries. Future work includes applying the flow to situations where layout-dependent DFM and process variation objective functions are also optimized     

Identification of hidden Markov models for ion channel currents.III. Bandlimited, sampled data

For pt.II. see ibid., vol.46, p.1916-29 (1998). Hidden Markov models (HMMs) have been used to model single channel currents as recorded with the patch clamp technique from living cells. Continuous time patch-clamp recordings are typically passed through an antialiasing filter and sampled before analysis. In this paper, an adaptation of the Baum-Welch weighted least squares (BW-WLS) algorithm called the H-noise algorithm is presented to estimate the HMM and noise model parameters from bandlimited, sampled data. The effects of the antialiasing filter and the correlated background noise are considered in a metastate or vector HMM framework. The “correlated emission probability”, which plays a central role in the algorithm, is redefined to consider the noise correlation in successive filtered, sampled data points. The performance of the H-noise algorithm is demonstrated with simulated data     

CYTOCENTERING: a novel technique enabling automated cell-by-cell patch clamping with the CYTOPATCH chip

Automats for patch clamping suspended cells in whole-cell configuration must (1) bring isolated cells in contact with patch contacts, (2) form gigaseals, and (3) establish stable intracellular access that allows for high quality recording of ionic currents. Single openings in planar substrates seem to be intriguing simple solutions for these problems, but due to the low rate of formation of whole-cell configurations we discarded this approach. Single openings are not suited for both attracting cells to the opening by suction and forming gigaseals with subsequent membrane rupture. To settle the three tasks with a mechanical microstructure we developed the socalled CYTOCENTERING technique to apply to suspended cells the same operation sequence as in conventional patch clamping. With this method we immobilized selected cells from a flowing suspension on the tip of a patch pipette by suction with a success rate of 97% and formed gigaseals with a success rate of 68%. Subsequent whole-cell recordings and intracellular staining with Lucifer yellow proved the stable access to the cytoplasm. Currently, a chip with an embedded suction opening in glass surrounding the microstructured contact pipette is under development. The processing of this CYTOPATCH chip is compatible to large-volume production. The CYTOPATCH automat will allow for fully automated, parallel, and asynchronous whole-cell recordings.     

pn结泄漏电流对高温集成MOSFET交流性能的影响

分析了漏源pn结泄漏电流对高温MOS模拟集成电路中、工作在零温度系数(ZTC点)的MOSFET交流参数的影响。研究结果表明,pn结扩散电流对高温MOSFET的交流性能有极大的影响,而产生电流的影响则可以忽略不计。减小泄漏电流对高温MOSFET交流性能影响的重要方法是增加衬底掺杂浓度。还给出了漏源pn结泄漏电流和工作在ZTC点的漏源电流最大允许比例的计算公式。     

带温度补偿的6H-SiC PMOS模拟与分析

提出了一个在较宽温度范围内能精确描述6H-SiC PMOS性能的器件模型。该模型将阈值电压、沟道迁移率、体漏电流、源漏薄层电阻的温度效应等效为相应的补偿电流源,并计入界面态电荷高斯分布模型及体内Poole-Frenkel效应。模拟结果表明,阈值电压是引起高温条件下输出电流变化的主要因素,同时随着温度的升高,由于体内缺陷的存在导致体漏电流所占比例不断增大,逐渐成为Ids的重要组成部分。     

Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity

Leakage power is becoming the dominant component of chip power consumption with continued CMOS scaling. An important but commonly unnoticed fact is that leaky transistors act as resistors that help dampen the mid-frequency power supply noise. This paper focuses on the damping effect of various on-chip current components including the leakage current which becomes significant in scaled technologies. By developing physics-based damping models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. The proposed models were validated in a 32-nm predictive CMOS technology under process–voltage–temperature (PVT) variations. Examples on large circuits such as SRAM caches are shown to illustrate the application of the proposed model. Simulation results show that the leakage induced damping effect can compensate the speed degradation at high temperatures by 7% or offer 61% saving in decap area and leakage power.      

Impact of super-steep-retrograde channel doping profiles on theperformance of scaled devices

Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L_gate and the same off-state leakage current I_off, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar