30Gbit/s并行光接收模块

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

30Gbit/s Parallel Optical Receiver Module

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

40 Gbit/s differential distributed modulator driver realised in 80 GHz SiGe HBT process

A 40 Gbit/s, fully differential distributed SiGe HBT driver is presented. The IC is realised in a low-cost 80 GHz production process, and is intended to operate as a modulator driver in a 40 Gbit/s fibre-optic communication system. Resulting from the differential chip architecture, no off-chip low-frequency transmission line termination networks are required, which significantly alleviates the chip mounting process. Mounted in a coaxial test fixture, an eye opening of 2 1.25 V_pp at 40 Gbit/s operation is measured.     

Optical self-homodyne DPSK transmission at 1 and 2 Gbit/s over 86 km of fibre

Optical self-homodyne DPSK transmission has been achieved at 1 and 2 Gbit/s data rates with respective receiver sensitivities of ?34.4 dBm and ?32.4 dBm at 10?9 BER. No dispersion penalty was observed after transmission through 86 km of optical fibre with 17 ps/?m/km dispersion at the operating wavelength of 1.53 ?m.     

4 Gbit/s pseudo-noise generator using GaAs MESFETs

A multiplexing gate using GaAs MESFETs is described and operation up to 4 Gbit/s is demonstrated. A 2 Gbit/s pseudo-noise generator which can deliver NRZ or RZ signals has been implemented with this circuit; the corresponding output sequences are shown.     

Low-power 100 Gbit/s selector IC using InP/InGaAs DHBTs

A low-power 100 Gbit/s selector IC using InP DHBTs, which provides excellent high-frequency characteristics at a low bias condition, is reported. A novel design technique, which assists high-speed operation under a low supply voltage condition, is used. The selector IC achieves 100 Gbit/s operation with a power consumption as low as 345 mW.     

2.5 Gbit/s multifunctional CMOS transceiver for chip-to-chip optical link

A novel multifunctional transceiver for chip-to-chip optical interconnects operating at 2.5 Gbit/s is proposed, which shares a common block between a receiver and a transmitter. This transceiver provides four conversion functions - electrical-to-optical, optical-to-optical, optical-to-electrical, and electrical-to-electrical - depending on the selection switch on a single chip. The whole chip integrated in 0.18 /spl mu/m CMOS occupies an area measuring 0.82/spl times/0.82 mm/sup 2/.     

Silicon bipolar IC for PRBS testing generates adjustable bit ratesup to 25 Gbit/s

For the first time, a completely integrated pseudo-random pattern generator providing adjustable bit rates up to at least 25 Gbit/s without additional external multiplexing is presented. The sequence length is 2ⁿ-1. The application of the monolithic Si bipolar IC serves as a single chip measurement instrument for pseudo-random binary sequence (PRBS) generation required for the characterisation and development of high-speed components used in future optical fibre communication systems. Only three external microwave components are needed for operation: a clock generator, a power divider and a phase shifter. The chip is realised in an advanced implanted base silicon bipolar technology     

10Gbit/s并行光收发模块在万兆以太网的应用

介绍了万兆以太网技术（10 gigabit ethernet technology) . 万兆以太网使用以太网结构实现10Gbit/s点对点传输，距离可达到40km，使以太网的应用从局域网扩展到城域网和广域网. 重点介绍了万兆以太网的功能结构、分层结构、物理传输介质和甚短距离（very short reach）网络传输的并行光传输系统在万兆以太网方面的应用.     

High sensitivity 5 Gbit/s optical receiver module using Si IC and GaInAs APD

A 5 Gbit/s optical receiver module was developed by using a wideband transimpedance Si IC and a high gain-bandwidth product GaInAs APD. A 6 GHz bandwidth Si IC utilising a f/sub t/=20 GHz Si MMIC process, bare chip mounting of a Si IC and an APD to minimise parasitic capacitance, made it possible to realise high speed operation and high receiver sensitivity of -31.8 dBm.<>     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

基于130 nm CMOS工艺的5 Gbit/s 10:1并串转换芯片

介绍了一种基于GSMC 130 nm CMOS工艺的高速率低功耗10:1并串转换芯片。在核心并串转换部分,该芯片使用了多相结构和树型结构相结合的方式,在输入半速率时钟的条件下,实现了10路500 Mbit/s并行数据到1路5 Gbit/s串行数据的转换。全芯片完整后仿真结果显示,在工作电压(1.2±10%)V、温度-55~100℃、全工艺角条件下,该芯片均可正确完成10:1并串转换逻辑功能,并输出清晰干净的5 Gbit/s眼图。在典型条件下,芯片整体功耗为25.2 mW,输出电压摆幅可达到260 mV。     

Demonstration of 20 Gbit/s all-optical logic XOR in integratedSOA-based interferometric wavelength converter

The results of optical logic exclusive-OR (XOR) at up to 20 Gbit/s in an integrated SOA-based Mach-Zehnder interferometer are presented. For the first time, to the knowledge of the authors, BER measurements are demonstrated on 10 Gbit/s optical logic XOR, with zero penalty. In addition. For the first time 20 Gbit/s all-optical XOR, with an integrated device that allows simple, stable, and efficient operation, is demonstrated     

10Gbit/s XFP光模块的设计

文章介绍了应用于光网络系统的10Gbit/s XFP(小型化可热插拔)光模块的基本原理以及光收发模块的设计,采用了CDR(时钟数据恢复)、APC(自动功率控制)、LA(限幅放大器)和发射驱动集成的主芯片GN2010EA,与传统设计相比不仅降低了设计成本,而且降低了设计的复杂度。测试结果表明,该模块在宽的温度范围内能保持稳定的光功率和消光比,并且指标满足ITU-T标准的要求,符合10Gbit/s光模块设计要求。     

20 Gbit/s, 1.55 μm strained-InGaAsP MQW modulator integrated DFBlaser module

The high-speed (20 Gbit/s) and highly efficient (2 V peak to peak for a 22 dB on/off ratio) operation of an MQW integrated electroabsorption modulator/DFB laser module is demonstrated. Output power from the module is over +3 dBm in the pigtailed singlemode fibre. To the authors' knowledge, this is the first report of 20 Gbit/s operation with a monolithically integrated light source     

First demonstration of simultaneous demultiplexing from 40 Gbit/sinto two channels of 20 Gbit/s by SOA-based all-optical polarisationswitch

Simultaneous demultiplexing from 40 Gbit/s data signal into two channels of 20 Gbit/s using semiconductor optical amplifier (SOA) based all-optical polarisation switch has been demonstrated. Error-free operation was confirmed with no power penalty. This is the first experimental demonstration to prove the full-switching capability of the SOA-based Mach-Zehnder interferometer (MZI) all-optical switch at such a high bit rate regime     

56 Gbit/s analogue PLL for clock recovery

A clock-recovery circuit is reported that employs a phase-locked loop (PLL) at 56.88 Gbit/s, and is demonstrated by locking to a 28.44 GHz sinusoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences. To the knowledge of the authors, this is the first demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s     

1.25 Gbit/s光接收机限幅放大器

文章介绍了采用0.35 μm双极型互补氧化物半导体(BiCMOS)工艺制作的光纤通信用低功耗的1.25 Gbit/s限幅放大器,其电路采用3.3 V单电源供电,电路增益可以达到70 dB,功耗为20 mW,在27 dB的输入动态范围内,可以保持800 mV的恒定输出摆幅.整个芯片的面积为1.30 mm×0.75 mm.     

5 V, 10 Gbit/s optical receiver module using Si-bipolar IC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 μm Si-bipolar technology. The module exhibits sensitivity of <-16 dBm for 10 Gbit/s data with an input dynamic range >15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V     

160 Gbit/s SOA all-optical wavelength converter and assessment of its regenerative properties

The retiming and reshaping properties of a 160 Gbit/s all-optical wavelength converter based on a semiconductor optical amplifier gating delay interferometer configuration is investigated. 160 Gbit/s operation is performed with as little as -3.5 dBm input signal.