VLSI in picture coding

Recent LSI technology development for motion video coding is described briefly. The standard coding algorithms discussed recently are based on interframe coding with motion compensation and DCT (Discrete Cosine Transform). LSIs for realizing the signal processing functions are shown as functions of integration scale and chip area. Custom design LSI chips for the interframe encoder and decoder, meeting the H.261 and MPEG standards, are shown. Also, progress of programmable video signal processors (VSP) are overviewed.     

VLSI in picture coding

Recent LSI technology development for motion video coding is described briefly. The standard coding algorithms discussed recently are based on interframe coding with motion compensation and DCT (Discrete Cosine Transform). LSIs for realizing the signal processing functions are shown as functions of integration scale and chip area. Custom design LSI chips for the interframe encoder and decoder, meeting the H.261 and MPEG standards, are shown. Also, progress of programmable video signal processors (VSP) are overviewed.     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

Single-chip baseband waveform generator CMOS-LSI for quadrature-type GMSK modulator

A single-chip baseband waveform generator CMOS-LSI has been fabricated for use in the quadrature-type GMSK modulator, which is suitable for application to digital mobile communications. The LSI employs digital signal processing in realising such functions as Gaussian baseband filtering and phase integration. Digital/analogue convertors and auxiliary circuits, such as an internal-clock generator and carrier frequency adjuster, are also integrated onto the same chip. The LSI operates well below a bit rate of 110 Kbit/s when the power supply voltage is 5 V.     

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low powermotion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAM's, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45×12.45 mm² chip with 0.35-μm CMOS and triple-metal layer technology are integrated 3.1 M transistors     

Low-power video encoder/decoder chip set for digital VCRs

This paper describes the realization of a video encoder/decoder chip set for the consumer use digital video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DV) format or decode the DV format signal into a component video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-μm 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-μm CMOS technology, contains about 500 k transistors on 71 mm² and 79 mm² die, respectively     

A 20 kbit associative memory LSI for artificial intelligencemachines

A 20 kb (512 words×40 b) CMOS associative-memory LSI is described. This LSI performs large-scale parallelism for highly efficient associative operations in artificial intelligence machines. Relational search, large-bit-length data treatment, and quick garbage collection are realized on the single-chip associative-memory LSI. A cell array structure has been designed in order to reduce the chip area. A newly designed simple accelerator circuit allows for high-speed search operations. The LSI is fabricated using 1.2 μm double-aluminium-layer CMOS process technology. 284000 devices have been integrated on a 5.3×7.9 mm² chip. The measured minimum cycle time and power dissipation at 10 MHz operation are 85 ns and 250 mW, respectively. The associative memory, with its highly efficient associative operation capabilities, promises to be a large step toward the development of high-performance artificial intelligence machines     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

A picosecond-accuracy, 700-MHz range, Si bipolar time intervalcounter LSI

A picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems is described. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5 K gate array LSI by developing fully digitally processes heat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, ±3-ps linearity, zero-skew offset of ±2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

CMOS video filters using switched capacitor 14 MHz circuits

In order to realize self-contained analog video LSI, video band switched-capacitor (C) filters, including a two-dimensional filter, have been experimentally fabricated. By using 2-/spl mu/m/spl middot/CMOS technology and high-speed/high-precision circuits, an LSI clock rate of 14 MHz, signal swing of 2 V p-p with a single 5-V supply, random noise S/N of 60-70 dB p-p/r.m.s at LSI output, and power dissipation of less than 5 mW per amplifier have been achieved. Single-stage cascode amplifiers are extensively used to attain video band speed. Neutralization is introduced into fully differential filters to improve their frequency response.     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors     

A Single‐Chip Video/Audio CODEC for Low Bit Rate Application

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single‐chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio signal processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardwired solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is 9.02 mm ×9.06 mm which is fabricated using 0.5 micron 3‐layer metal CMOS technology.     

Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI)

An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser power and needs significantly less area for its implementation.Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 × 3 mm² including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks.A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS.The counter design could easily be substituted as a sub-system/building block or cell in any MOS LSI system design where it makes a part of it.     

A self-learning neural network chip with 125 neurons and 10 Kself-organization synapses

A learning neural network LSI chip is described. The chip integrates 125 neuron units and 10K synapse units with the 1.0 μm double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50 μs learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2 μs. This chip consumes less than 7.5 W     

An adjustment-free single-chip video signal processing LSI for VHSVCR's

The authors have developed an adjustment-free single-chip video signal processing large scale integration (LSI) for VHS VCR's. This LSI's adjustment-free system was realized by using automatic feedback loop circuits. The complementary high-speed switch circuits play an important role in this system. It was possible to realize the complementary high-speed switch circuits, because this LSI has been fabricated with 2 μm bipolar process. This paper describes how the LSI has succeeded in being adjustment-free on frequency modulation (FM) carrier frequency/deviation and output video signal amplitude     

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

Computer-aided design of an n-MOS custom IC-“Subscriber Chip” of the 32-lines microprocessor based PAX (private automatic exchange) system

A 40-pin custom IC-“Subscriber Chip” of the subscriber module of the Intel 8085A microprocessor based PAX system (32P₄-32 lines and four parallel conversations) has been designed using CAD techniques. The chip design is based on the LOCOS n-MOS(E-D) process, 8 micron minimum feature size geometries, λ-based design rules and the cell based design approach.DIF-POL contact for the gate-source interconnection of the depletion load transistors has been made with the buried contacts. System routing has been done on two layers: metal and polysilicon/diffusion. Single metal layer has been used for power and ground routing having interdigitated structure.Chip has also been designed for its testability analysis based on the chip partioning approach. Two phases of the testing have been evolved and the test pattern generation sequences got fully integrated with the chip layout.Latest CAD techniques: Applicon AGS/860 VLSI Interactive Graphics Design System, MOS circuit simulation program MSINC and Design Rule Check program (DRC) have been used for the design and chip layout. The entire chip has been laid-out in the area of 3.35 × 3.35 mm² integrating around 500 components including test devices and structures for the evaluation of devices and process parameters. The Electromask pattern generation (PG) tape has been prepared for making chrome masks.A set of eight masks are to be used in the fabrication of the chip and encapsulated in 40 pin LSI package. The subscriber chip makes the PAX system design simple and reliable.     

Reliability of MOS LSl circuits

MOS LSI circuits share many of the reliability problem associated with discrete semiconductors and medium-scale integrated circuits. However, because of the added complexity, larger chip size, and higher densities of MOS LSI circuits, different approaches are needed. A close working relationship between the designer, manufacturer, and user-the reliability triangle--is needed to generate the manufacturing controls, testing methods, and reliability assessment procedures and to optimize the performance and reliability of the MOS LSI circuits. Using this approach, the MOS LSI circuit, having more functions per external connection, can provide a more reliable system than one of equal complexity, based on discrete devices or less complex integrated circuits. Specific areas of reliability such as pattern sensitivity, manufacturing controls, assembly, packaging, and electrical testing have also been discussed.