基于IEEE 1451.2网络化智能传感器的应用研究

介绍最新的总线标准IEEE1451,该标准定义了网络适配处理器(NCAP)和智能传感器接口模型(STIM),为研究解决通用智能传感器的设计开发问题提供了一个可以共同遵循的基础,使得智能传感器的即插即用成为可能;根据IEEE1451.2模块TMI1451.2-SC平台,结合实际监控领域的要求,设计和配置了网络化智能传感器的电子数据表单(TEDS)。     

基于IEEE1451接口的智能网络传感器设计

提出一种基于IEEE1451.2和IEEE1451.4相结合网络传感器的接口,有效地解决了固定通道数的数据采集系统,频繁进行热插拔情况下统一接口设计的问题.所有传感器能以任何组合插入任何一个或多个数据采集通道.设计了基于IEEE1451.2的TEDS,最后详细介绍了以Pt100为变换器的温度传感器的校正引擎的设计.实验证明,该校正方法能提高测量精度0.1～0.4℃     

基于IEEE 1451.3的IPv6网络传感器设计

针对网络环境下的信息获取,研究了传感器网络和IPv6网络之间的融合。结合IEEE 1451网络传感器的设计思想,设计了一个以单总线传感器为基础、以IEEE 1451．3为接口标准的即插即用的IPv6网络传感器。采用MAXIM公司的DS80C400作为网络接口控制器．使传感器网络成功地接人IPv6网络。本文着重介绍了网络控制器的开发,即单总线接口、IPv6网络接口的开发以及虚拟TEDS的设计。     

A Universal Transducer Interface for Capacitive and Resistive Sensor Elements

This paper presents a new universal transducer interface.This interface, which is read out by a microcontroller, servicesthe following sensor elements: capacitors, platinum resistors,thermistors, resistive bridges and potentiometers. The A/D conversionis based on a first-order oscillator. A combination of classicaland some new measurement techniques has been applied on a singlechip to obtain high accuracy, good long-term stability and areduction of the effects of interference and parasitic elements.The circuit has been fabricated in a 0.7 µm CMOSprocess. The main test results are: an accuracy of 10–15bits and a resolution up to 16 bits while the measurement timeis in the range 1–100ms. These results hold over the temperaturerange –20°C to 80°C. Calibrationof the electronic part is not required. The number of externalcomponents has been kept to a minimum.     

基于IEEE标准的智能监测系统集成研究

文中针对综合监测系统传感器之间接口兼容及网络互操作性问题,基于IEEE1451智能传感器接口和CAN总线技术,对一款开放式、“即插即用”的智能监测系统集成研究。结合IEEE1451．2和IEEE1451．4接口标准,完成执行器模块（STIM）、TII接口电路及传感器电子数据表单（TEDS）方案的设计;基于CAN总线技术完成网络适配器（NCAP）硬件模块、容错协议和优先晋升算法的设计。节点通信实验分析表明,系统可靠性高,实时性良好。     

宽带接入网的体系结构

讨论了宽带接入网的进展 ,论述了宽带接入网及其用户 -网络接口 (U NI)、业务节点接口 (SNI)和电信网管理(Q3)接口 ,并总结了宽带接入网的主要功能以及宽带业务节点接口 (VB5 )标准的主要原则。还例举了多媒体接入体系的实例及其最新发展。     

An integrated improved CCII topology for resistive sensor application

In this paper a novel low voltage low power topology of second generation current conveyor (CCII) is presented. The internal CCII stages have been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. As an application example, the here proposed CCII, designed in standard CMOS technology (AMS 0.35 μm), has been used to design an integrated resistive sensor interface, showing the capability of compensating the non idealities of passive and active components. Preliminary and post-layout simulations show an excellent linearity for what concerns sensor sensitivity.     

Adaptable Interface Circuits for Flexible Monitoring of Temperature and Movement

This paper describes the development of two small dataacquisition chips with on board interface circuits for a miniaturisedcapacitive accelerometer, as well as for a set of thermistors.They are intended for use in biomedical, implantable telemetryapplication, requiring low power and small size for the entiresystem. Beside the typical aspects of circuit design, emphasisis also put on the overall system design, to pinpoint to thetypical constraints of the application. This leads to one ofits most important features: the flexible specifications, allowinga user-defined setting of the monitoring windows, after the deviceis manufactured. In the paper this concept is explained, andan example of a hard-wired system and a software controlled systemare given.     

Current conveyor-based differential capacitance analog interface for displacement sensing application

A current conveyor-based analog electronic interface for differential capacitive sensors is here shown. The read-out circuit that utilizes second generation Current Conveyors (CCIIs) as active blocks is able to evaluate differential capacitive variations performing a capacitance-to-voltage conversion. This solution has been implemented both in a discrete element board and as integrated version in a standard 350  nm CMOS technology. Simulations and experimental results have shown a linear input/output characteristic and a good agreement with theoretical expectations, being the former performed for both the designed solutions, whereas the latter only for a discrete prototype board (employing a low cost commercial component (AD844). Sensitivity and resolution data on a practical case-study of a displacement sensor are constant and their values are satisfactory. Both simulated and measured results make the proposed architecture a good candidate as first stage of analog front-ends to be employed in differential capacitive instrumentation.     

无线传感器网络节点的硬件平台可扩展研究

为了实现扩展节点功能、添加硬件部件时可以在现有节点上直接添加,而无需设计新的节点。无线传感器网络节点的分布式体系结构采用IEEE1451．2标准中即插即用的构造方法,并给出具体的硬件和软件实现方法,得到了硬件平台可扩展的结论。这样的节点具有完全统一的外部接口和多智能体结构,并且传感器模块能够即插即用,可以在不同应用环境中,选择不同的组件自由配置系统。     

基于CORBA的传送网EML-NML接口研究与实现

文章系统地介绍了电信管理网（TMN）管理体系结构和各功能层接口参考点的关系。分析了现有网元管理层-网络管理层（EML-NML）接口Q3标准在面向对象的分布式环境下的不足以及通用对象请求代理体系结构（CORBA）在分布式应用环境下的优势。详尽地阐述了CORBA技术在EML-NML接口中的应用,以及传送网管理平台上基于CORBA的EML北向接口实现体系结构,并提出了一种基于CORBA技术的通用EML-NML接口设计实现方案,最后给出了以ORBIX6．1为CORBA实现平台的TMN总体运行方案。     

简易RS-232/RS-485智能转换器

介绍了一种简易的RS-232/RS-485智能转换器的设计方法,并给出了具体的硬件实现电路。     

fMRI-BCI： a Review

Functional magnetic resonance imaging （fMRI） is a new tool for brain-computer interface （BCI）. This paper presents an overview to fMRI-BCI. Our attention is mainly put on the methods of signal acquisition, signal preprocessing, and signal analysis of basic fMRI-BCI structure. The available softwares and the applications of fMRI-BCI are briefly introduced. At last, we suggest focusing on some technologies to make fMRI-BCI more perfect.     

fMRI-BCI: a Review

Functional magnetic resonance imaging (fMRI) is a new tool for brain-computer interface (BCI). This paper presents an overview to fMRI-BCI. Our attention is mainly put on the methods of signal acquisition, signal preprocessing, and signal analysis of basic fMRI-BCI structure. The available softwares and the applications of fMRI-BCI are briefly introduced. At last, we suggest focusing on some technologies to make fMRI-BCI more perfect.     

COSMOS: A Middleware for Integrated Data Processing over Heterogeneous Sensor Networks

With the increasing need for intelligent environment monitoring applications and the decreasing cost of manufacturing sensor devices, it is likely that a wide variety of sensor networks will be deployed in the near future. In this environment, the way to access heterogeneous sensor networks and the way to integrate various sensor data are very important. This paper proposes the common system for middleware of sensor networks (COSMOS), which provides integrated data processing over multiple heterogeneous sensor networks based on sensor network abstraction called the sensor network common interface. Specifically, this paper introduces the sensor network common interface which defines a standardized communication protocol and message formats used between the COSMOS and sensor networks.     

利用CDMA2000 A1p接口实现IP基站的接入

移动运营商为发挥已经有资源的效益而沿3G路线演化是必然选择，从发展的角度看3G应用，不论是语音、数据还是多媒体的承载方式，核心网全IP化是大势所趋。以CDMA2000为例，应用3GPP2的最新A接口标准，提出一种基于IP基站进行接入的一种实现方案，并就相关问题进行讨论。     

Low-Cost CMOS Interface for Capacitive Sensors and Its Application in a Capacitive Angular Encoder

A low-cost CMOS integrated interface for capacitivesensors is presented. The interface is composed of two separatechips: a capacitance-controlled oscillator and a selector, whichresult in a structure that is able to measure several capacitancesaccurately and has a microcontroller-compatible output. In thisinterface, even large parasitic capacitances of up to 3 nF betweenthe terminals of the capacitor to be measured and ground areallowed. Prototypes of the interface chips have been fabricatedin a 0.7-µm CMOS process. The frequency of theoscillator amounts to 90 kHz. For the capacitance measurement,the interface has a resolution of 11.3 ppm and a nonlinearityof 300 ppm over a measurement range of 2 pF. In this paper, alsothe application of the interface in an accurate capacitive angularencoder is discussed.     

The use of interface-sensitive test structure comprising of shallow trench isolation as a tool for analyzing the quality of Si–SiO2 interfaces

Si–SiO₂ interface plays an important role in the performance of VLSI devices. Minor changes in interfaces, which cannot be detected by direct measurements, can alter the electrical performance of sensitive devices, for example CMOS Image Sensors (CIS). In such cases, there is a significant time delay (up to several months) between the processing of the interface and the monitoring of its quality. In what follows, we describe herein a method for analyzing the quality of Shallow Trench Isolation (STI) interface based on analyzing the performance of a simple STI interface named as Sensitive High Resistance Structure (SSHR). This testing device can be introduced in the production line as a “short loop” monitoring device. The method was demonstrated by comparing various cleaning treatments while analyzing the resistivity and breakdown voltage of the SSHR device. Results were correlated with STI-sensitive final products such as CIS and Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistors.     

Editorial

Future integrated microsystems will benefit significantlyfrom progress in the VLSI field. Two key elements will boostthe implementation of new micro-integrated architectures: progressin batch-manufactured silicon sensors and the introduction ofnew circuit techniques for designing interface circuits. Thesetwo factors will be essential in favoring the transition fromthe present research driven speculations to customer drivenactivities. This paper discusses the key issues in realizingmicrosensors and the most suitable circuit techniques for interfacingand processing their output signals. A number of examples ofintegrated structures will illustrate present problems and possiblesolutions.