A new built-in screening methodology to achieve zero defects in the automotive environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring.     

A New Built-In Defect-Based Testing Technique to Achieve Zero Defects in the Automotive Environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes control logic, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed test procedure are described in very detail and illustrated by circuit simulation.     

Ultrathin gate oxide reliability: physical models, statistics, andcharacterization

The present understanding of wear-out and breakdown in ultrathin (t_ox < 5.0 nm) SiO₂ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed     

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH₄) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.     

Importance of multi-temp testing in automotive qualification and zero defects program

For automotive qualification of Integrated circuits (ICs), multi-temp testing is required by AEC-Q100. In this paper, we demonstrate the importance and necessity of this multi-temp testing in automotive qualification and zero defects program.During the qualification of one of our new products, we found that all samples could pass electrical testing at room temperature after high temperature operating life test, but a few of them failed at hot temperature. One transistor in the circuit was found to have large leakage current. Only at hot temperature, this leakage current was increased (>50 μA) and the fail was detected during hot electrical testing. Root cause was identified and design error is corrected before the release of the product. No failures are observed anymore.     

Design-for-Manufacture for Multigate Oxide CMOS Process

Design-for-manufacture (DFM) for thick gate oxide layout in a dual gate oxide product is investigated. Careless placement and layout for thick gate oxide transistors in the multigate oxide chip can cause significant yield loss. The root cause of the yield loss is that the thick gate oxide can impact the uniformity of the adjacent thin gate oxide thickness. Further experiments' results show that the optimization of thick gate oxide transistor layout for the same product can improve the yield. Besides tweaking the gate oxide etching process to overcome the difficulty of multi oxide product manufacture, the guidelines for a good gate oxide layout practice are provided to facilitate the manufacture.     

Gate Oxide Short Defect Model in FinFETs

FinFET technology is one of the most promising candidates in replacing planar MOSFET beyond the 22 nm technology node. However, the complexity of FinFET manufacturing process has caused challenges in reliable device testing. Gate oxide short (GOS) is one of the dominant defects that has significant impact on circuit reliability. In this paper, we present a GOS defect model for FinFETs by introducing the defect as a pinhole in the gate oxide of a triangular fin shape structure. The pinholes are represented by small cuboid cuts of various sizes on the fin top and sidewalls along the channel. The 3D Sentaurus TCAD simulation results in the development of an analytical GOS defect model that can be used in circuit-level fault modeling, which leads to generating more realistic test patterns.     

A detailed analysis of CMOS SRAM's with gate oxide short defects

Using a model of gate oxide short defects, previously developed and validated experimentally, we investigate the behavior of CMOS SRAM memories having this defect. Faulty behaviors caused by gate oxide shorts are characterized classifying those that may cause a logic malfunction and those that degrade the memory operation without causing a logic error. Merits of SRAM test algorithms to detect gate oxide shorts are analyzed, identifying which are effective in terms of coverage and test cost     

汽车电子产品的零缺陷检测

汽车电子行业,由于高质量和可靠性要求,越来越多的客户追求零缺陷质量,零缺陷实现方法成为越来越多汽车电子制造商研究的课题.从产品设计实现、产品制造以及产品最终测试过程中,本文主要论述在产品测试检测以及数据分析中如何实现零缺陷,以及提升可靠性的老化筛选方法,有效地避免和筛选潜在失效产品的产生和流出,确保客户手中产品的零缺陷...     

New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability?

This paper will start with a discussion of why probe yield (the number of good chips per silicon wafer) is so important to financial success in integrated circuit manufacturing. Actual data will be quoted and a numerical example shown. A simple model will be given to demonstrate the main factors influencing yield and the relationship between yield and reliability of the final product. In the last few years a range of new tools have been deployed in manufacturing, and these have accelerated the pace of yield improvement, thus increasing competitive pressures. These tools will be described, along with examples of their use. Topics will include in-line inspection and control, automatic defect classification and data mining techniques. A proposal is made to extend these tools to the improvement of reliability of products already in manufacturing by maintaining absolute chip identity throughout the entire wafer fabrication, packaging and final testing steps.     

Sudden failures associated with the gate oxide of CMOS transistors

Sudden failures appearing during static gate bias — temperature aging of CMOS transistors are investigated in this paper. Shorts between the gate and substrate as well as open gate circuits are found to be failure modes appearing during testing. The subsequent failure analysis reveals that the reaction between the aluminium and gate oxide is the failure mechanism, while defects in P⁺-diffusion regions (which are transferred onto the gate oxide) are the cause of the observed failures.     

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.     

Failure mechanisms in advanced BCD technology during reliability qualification

During the qualification of a new Advanced Bipolar, CMOS, DMOS (A-BCD) technology some typical failure modes were observed in this SOI process. After a short introduction of the technology and its areas of application three different failure modes will be discussed. The failures initiated during HTOL test are localized with standard PEM/OBIRCH analysis techniques. Main focus will be on the physical defects at the origin of the fail and the different techniques to reveal them. The failures are observed within the Shallow Trench Isolation (STI) module of the High Voltage components and along the edge of the Medium Trench Isolation (MTI). The root causes and the possible corrective actions will be discussed when applicable.     

Imaging of the lateral GOI-defect distribution in silicon MOS wafers with lock-in IR-thermography

Yield and reliability of MOS devices are strongly affected by crystal-originated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the density, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias pulse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2 V is applied and the local temperature variation caused by the leakage current through the broken GOI defects is imaged by lock-in IR-thermography. This technique has been used to image the GOI defect distribution across 8′′ Czochralski wafers. Various lateral variations of the defect distribution have been confirmed.     

CMOS gate oxide defects induced by pre-gate plasma process

Plasma processes used for strip resist and etch oxide in CMOS technologies may degrade the quality of the silicon surface if it is protected of the plasma by a too thin oxide capping. Using AFM measurements, we have identified this degradation as a silicon roughness increase. The degradation mechanism can be understood like an uncontrolled plasma oxidation of the silicon. Next, if gate oxidation is performed after such plasma treatments, the gate oxide will show defects at the oxide/silicon interface. The consequence will be a poor reliability when negative electrical bias is applied on CMOS gate. Finally, the damaged silicon layer can also be efficiently removed by performing a sacrificial oxidation.     

A simple wafer-level measurement technique for predicting oxidereliability

A new wafer-level measurement technique, the differential gate antenna analysis, has been developed to detect weaknesses in sub-micrometer oxide. This simple technique involves the use of dual antenna structures with different gate oxide areas but the same antenna area ratio. The critical parameter is the difference in their failure levels. It is shown that such a differential measurement of antenna failures correlates with product failure during accelerated life testing. The differential antenna structures are thus proven useful for real-time wafer-level monitoring of oxide reliability     

ASIC reliability and qualification: a user's perspective

The process of qualifying an application-specific integrated circuit (ASIC) such as gate arrays of standard cells, that is used in product development at the IBM Rochester, Minnesota, development laboratory is reviewed. The emphasis is on reliability and its evaluation during the qualification process. The varying degrees of involvement in qualification activities that a supplier has had over the last few years are outlined. These qualification activities, such as technology qualification, specific part number qualifications, supplier process surveys, part construction analysis, and failure rate projections, are discussed. Postqualification expectations in terms of burn-in, reliability monitors, and reliability growth goals are also discussed     

Effects of burn-in stressing on radiation response of power VDMOSFETs

The effects of pre-irradiation burn-in stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed, and more considerable mobility reduction in unstressed devices have been observed, confirming the necessity of performing the radiation qualification testing after the reliability screening of power MOSFETs. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects. The buildup of oxide-trapped charge appeared to be almost independent of device pre-irradiation stress, while the buildup of interface traps was somewhat less pronounced in stressed devices. Passivation of interface-trap precursors due to diffusion of hydrogen related species (originating either from package inside or gate oxide adjacent structures) from the bulk of the oxide towards the interface has been proposed as a mechanism responsible for the suppressed interface-trap buildup in pre-irradiation stressed devices.     

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.This work is supported by the Ministry of Education of Spain (CICYT TIC 046/95).     

MMIC高温工作加速寿命试验失效机理分析

采用恒定功耗高温加速的试验方法,搭建了相关的试验系统,对高温工作寿命试验(HTOL)方法在功率GaAs MMIC领域的应用进行了一些探索。试验获得了对失效机理进行分析所需的失效数,所有样品的失效都是由同一原因引起的。通过监测数据和失效样品的分析,发现存在欧姆接触退化与栅金属下沉两种失效机理,但最终引起失效的机理单一,为栅金属下沉。