Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

Characterization of various alloying metal oxide nanoparticles embedded in HfOxNy as charge trapping nodes in nonvolatile memory devices

This work compares Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO alloying metal oxide nanoparticles (AMONs) that were individually embedded in HfO_xN_y high-k dielectric as charge trapping nodes. They were formed by chemical vapor deposition using Co/Mo, Co/Fe and Fe/Mo acetate, respectively, calcined and reduced in Ar/NH₃ ambient. The effects of various pre-treatments on Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO AMONs preparation were investigated. The results indicate that the larger charge trap density, larger memory window and better programming characteristics of Co_xMo_yO AMONs are attributable to their higher surface density and smaller diameter. The average collected charge in each Co_xMo_yO AMON is the smallest among three AMONs, revealing that a local leakage path is associated with the least charge loss. The main mechanism that governs the programming characteristics involves the trapping of holes.     

基于Si3N4的电荷俘获型存储器中氧缺陷的第一性原理研究

Based on first principle calculations, a comprehensive study of substitutional oxygen defects in hexagonal silicon nitride （β-Si3N4） has been carried out. Firstly, it is found that substitutional oxygen is most likely to form clusters at three sites in Si3N4 due to the intense attractive interaction between oxygen defects. Then, by using three analytical tools （trap energy, modified Bader analysis and charge density difference）, we discuss the trap abilities of the three clusters. The result shows that each kind of cluster at the three specific sites presents very different abilities to trap charge carriers （electrons or holes）： two of the three clusters can trap both kinds of charge carriers, confirming their amphoteric property; While the last remaining one is only able to trap hole carriers. Moreover, our studies reveal that the three clusters differ from each other in terms of endurance during the program/erase progress. Taking full account of capturing properties for the three oxygen clusters, including trap ability and endurance, we deem holes rather than electrons to be optimal to act as operational charge carriers for the oxygen defects in Si3N4-based charge trapping memories.     

High-density NiSi nanocrystals embedded in Al2O3/SiO2 double-barrier for robust retention of nonvolatile memory

NiSi nanocrystals of high density and good uniformity were synthesized by vapor–solid–solid growth in a gas source molecular beam epitaxy system using Si₂H₆ as Si precursor and Ni as catalyst. A metal–oxide–semiconductor memory device with NiSi nanocrystal–Al₂O₃/SiO₂ double-barrier structure was fabricated. Large memory window and excellent retention at both room temperature and high temperature of 85 °C were demonstrated.     

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

An ultrathin SiO₂ interfacial buffer layer is formed using the nitric acid oxidation of Si (NAOS) method to improve the interface and electrical properties of Al₂O₃/Si, and its effect on the leakage current and interfacial states is analyzed. The leakage current density of the Al₂O₃/Si sample (8.1 × 10^?9 A cm^?2) due to the formation of low‐density SiO_x layer during the atomic layer deposition (ALD) process, decreases by approximately two orders of magnitude when SiO₂ buffer layer is inserted using the NAOS method (1.1 × 10^?11 A cm^?2), and further decreases after post‐metallization annealing (PMA) (1.4 × 10^?12 A cm^?2). Based on these results, the influence of interfacial defect states is analyzed. The equilibrium density of defect sites (N_d) and fixed charge density (N_f) are both reduced after NAOS and then further decreased by PMA treatment. The interface state density (D_it) at 0.11 eV decreases about one order of magnitude from 2.5 × 10¹² to 7.3 × 10¹¹ atoms eV^?1 cm^?2 after NAOS, and to 3.0 × 10¹⁰ atoms eV^?1 cm^?2 after PMA. Consequently, it is demonstrated that the high defect density of the Al₂O₃/Si interface is drastically reduced by fabricating ultrathin high density SiO₂ buffer layer, and the insulating properties are improved.     

Impact of PDA temperature on electron trap energy and spatial distributions in SiO2/Al2O3 stack as the IPD in Flash memory cells

SiO_xN_y/high-κ dielectric stack will soon replace the conventional SiO_xN_y-based dielectric stacks in the future generations of flash memory cells. Characterizing and reducing electron traps in the high-κ layer is an important task, as the large trap density may limit the memory retention via the trap-assisted tunneling. Since the Post-deposition Annealing (PDA) has great impact on the microstructure of high-κ dielectric, it is important to understand how PDA affects the properties of electron traps, such as the trap density, energy and spatial distributions. It is demonstrated in this paper that, by using a recently developed two-pulse C–V measurement technique, the energy and spatial distributions of electron traps throughout the SiO₂/high-κ stack can be characterized, and PDA temperatures have different impacts on traps at different energy levels and spatial locations.     

Analysis of the stress and interfacial reactions in Pt/Ti/SiO2/Si for use with ferroelectric thin films

The microstructure of the Pt/Ti/SiO₂/Si structure has been investigated by scanning and transmission electron microscopy. Pt films of 100 nm thickness deposited by sputtering or evaporation onto unheated substrates gave complete coverage of the underlying Ti layer and showed a granular and faceted structure with grains ∼20 nm in diameter. They did not exhibit hillocks or surface TiO_x formation. X-ray diffraction was used to examine the film stress through use of the sin²ψ method with bulk values for the elastic constants (v=0.39, E=162 GPa). The as-deposited sputtered film had a compressive stress of ∼540 MPa, while the evaporated films had tensile stresses of ∼630 MPa. The films then received a 400°C rapid thermal anneal (RTA) for 90 s and a subsequent RTA of 650°C for 30s. Further investigation of the film stresses and microstructure were made after each annealing step. After the low temperature anneal, the film stress for the sputtered film became tensile. Plan-view sections examined by transmission electron microscopy (TEM) showed that the as-deposited sputtered films were dense but became porous after annealing. Initially, the evaporated films had a less dense microstructure, but were more stable with annealing. Little change in the stress for the evaporated film was observed after this initial low temperature annealing step. Additional annealing of the evaporated and sputtered samples caused complete consumption of the Ti layer including some TiO_x formation from the underlying SiO₂ layer and marked interaction with the Pt; however, little change in the stress was found. The surface of the Pt film revealed larger grains, but otherwise remained unaffected. The underlying phase changes were minimized once the Ti layer had reacted with the Pt. Due to the ratio of the layers, Pt:Ti of 2:1, the surface of the Pt was unaffected.     

Laser processing of Al2O3/a‐SiCx:H stacks: a feasible solution for the rear surface of high‐efficiency p‐type c‐Si solar cells

We explore the potential of laser processing aluminium oxide (Al₂O₃)/amorphous silicon carbide (a‐SiC_x:H) stacks to be used at the rear surface of p‐type crystalline silicon (c‐Si) solar cells. For this stack, excellent quality surface passivation is measured with effective surface recombination velocities as low as 2 cm/s. By means of an infrared laser, the dielectric film is locally opened. Simultaneously, part of the aluminium in the Al₂O₃ film is introduced into the c‐Si, creating p+ regions that allow ohmic contacts with low‐surface recombination velocities. At optimum pitch, high‐efficiency solar cells are achievable for substrates of 0.5–2.5 Ω cm. Copyright © 2012 John Wiley & Sons, Ltd.