快速热退火制备多晶硅薄膜的研究

采用等离子体增强化学气相沉积法(PECVD)沉积非晶硅薄膜,然后在快速热退火炉中进行退火。研究了升温速率、降温速率对晶化的影响。结果表明:退火中,升温速率越大,越不利于晶核的形成;降温速率较小时(100℃/60s),形成的晶粒尺寸较小,晶化情况较好,晶化率估算达64.56%。     

Rapid thermal annealing of neutron transmutation doped silicon

Rapid thermal annealing (RTA) of neutron transmutation doped Si wafers is shown to be an alternative to conventional furnace annealing. Measurements of resistivity and deep level transient spectroscopy (DLTS), demonstrated annealing on wafers with diameters up to 75 mm. A 4.5 kW incoherent-light RTA furnace was used. Evidence for crystalline slip was found but this did not appear to affect the results. The slip was more severe for the larger diameter wafers. Some results from a DLTS examination of a partially rapid-thermal-annealed wafer are presented.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

空位缺陷对Si薄膜热导率的影响

利用非平衡分子动力学方法研究了空位结构缺陷对Si薄膜热导率的影响。当温度在300K-700K之间变化时,热导率随着空位浓度的增加而降低,并且随着温度的升高空位浓度对热导率的影响以及同一空位浓度下温度对热导率的影响都在逐渐减弱。本文还利用Boltzmann输运理论对MD模拟进行验证,结果基本与其一致。同时理论方法还表明,空位缺陷对薄膜热导率的巨大影响归因于晶格应力的存在使点缺陷也发生散射作用的结果。     

Effects of vacancy structural defects on the thermal conductivity of silicon thin films

Vacancy structural defect effects on the lattice thermal conductivity of silicon thin films have been investigated with non-equilibrium molecular dynamics simulation.The lattice thermal conductivities decrease with increasing vacancy concentration at all temperatures from 300 to 700 K.Vacancy defects decrease the sample thermal conductivity,and the temperature dependence of thermal conductivity becomes less significant as the temperature increases.The molecular dynamics result is in good agreement with the theoretical analysis values obtained based on the Boltzmann equation.In addition,theoretical analysis indicates that the reduction in the lattice thermal conductivity with vacancy defects can be explained by the enhanced point-defect scattering due to lattice strain.     

Effect of Si/Ta and nitrogen ratios on the thermal stability of Ta-Si-N thin films

Ta-Si-N thin films were fabricated by using reactive magnetron cosputtering at different Si/Ta power ratios and nitrogen (N₂) to total gas (Ar + N₂) flow ratios (FN₂% = FN₂/(FAr + FN₂) × 100%). Both levels of high-vacuum furnace annealing (FA) and low vacuum rapid thermal annealing (RTA) were performed to investigate the thermal stability of films. The microstructure, morphology and electrical property of the Ta-Si-N thin films were characterized by grazing incidence X-ray diffraction, scanning electron microscope and four-point probe method, respectively. Ta-Si-N thin films at low FN₂% could endure temperature up to 900 °C for 1 h under high-vacuum FA at 6.5 × 10⁻³ Pa while their phase and morphology had changed under RTA at 750-900 °C for 1 min at 2.6 Pa. The resistivity increased with increasing both FN₂% and Si/Ta power ratios. However, the variation percentage of resistivity of Ta-Si-N films at high-temperature annealing decreased with increasing Si/Ta power ratio and inversely increased with increasing FN₂%. In brief, the thermal stability of Ta-Si-N films increased with increasing level of vacuum and Si/Ta power ratio. Increasing FN₂% and Si/Ta power ratio could enhance the thermal stability of films at RTA but also increased the resisitivity of films. Therefore, Ta-Si-N films prepared at 2 FN₂% and Si/Ta power ratio of 2/1 can be a good candidate for the application of diffusion barrier with low resistivity, low variation percentage and high stability of microstructure.     

Rapid thermal annealing of cerium dioxide thin films sputtered onto silicon (111) substrates: Influence of heating rate on microstructure and electrical properties

The impact of the heating rate (HR) of a Rapid Thermal Annealing (RTA) on the crystallinity and on the morphology of CeO₂ thin films has been investigated by Raman Spectroscopy (RS), Photoluminescence (PL), Scanning Electron Microscopy (SEM), Energy Dispersive Spectroscopy (EDS), and tapping mode Atomic Force Microscopy (AFM). The electrical properties of CeO₂ thin films have also been studied with the Conductive AFM mode. This paper highlights the importance of the heating rate value used during an RTA on crystalline quality, morphology and on the electrical properties of the CeO₂ layer. In fact, the best crystallinity with a good morphology and a high resistivity has been obtained for a CeO₂ layer sputtered on (111) Si substrate and post-annealed at 1000 °C for 30 s with an HR of 25 °C/s.     

Si基外延Ge薄膜及退火对其特性的影响研究

采用超高真空化学气相沉积(UHV-CVD)系统,用低温Ge缓冲层技术在Si衬底上外延了张应变Ge薄膜.扫描电镜(TEM)图表明Si基外延Ge薄膜拥有低的位错密度,原子力显微镜(AFM)测试Ge层表面粗糙度仅为1.2 nm.对Si基外延Ge薄膜进行了不同温度下的退火,并用双晶X射线衍射(DCXRD)曲线和Raman谱进行...     

Effects of annealing conditions on the properties of tantalum oxide films on silicon substrates

The formation of a SiO₂ layer at the Ta₂O₅/Si interface is observed by annealing in dry O₂ or N₂ and the thickness of this layer increases with an increase in annealing temperature. Leakage current of thin (less than 40 nm thick) Ta₂O₅ films decreases as the annealing temperature increases when annealed in dry O₂ or N₂. The dielectric constant vs annealing temperature curve shows a maximum peak at 750 or 800° C resulting from the crystallization of Ta₂O₅. The effect is larger in thicker Ta₂O₅ films. But the dielectric constant decreases when annealed at higher temperature due to the formation and growth of a SiO₂ layer at the interface. The flat band voltage and gate voltage instability as a function of annealing temperature can be explained in terms of the growth of interfacial SiO₂. The electrical properties of Ta₂O₅ as a function of annealing conditions do not depend on the fabrication method of Ta₂O₅ but strongly depend on the thickness of Ta₂O₅ layer.     

激光结晶a-Si:H SOI离子注入和快速退火

本文对激光结晶a-Si∶H SOI结构砷注入和快速退火行为作了研究.a-Si∶H激光结晶有Lp-LCR,OD,FCR-2,FCR-1四个结晶区.用剖面电镜观察了结晶区的结构.扩展电阻测量表明Lp-LCR区中有两种扩散机制,即杂质在晶粒体内扩散和沿缺陷扩散.OD区中有三种扩散形式,除有上述两种以外,还有沿缺陷的扩散.首次比较了沿晶界和缺陷的扩散速度.     

Effects of rapid thermal annealing on nitrided gate oxide grown on 4H-SiC

The electrical characteristics of thermally nitrided gate oxides on n-type 4H-SiC, with and without rapid thermal annealing processes, have been investigated and compared in this paper. The effects of annealing time (isothermal annealing) and annealing temperature (isochronal annealing) on the gate oxide quality have also been systematically investigated. After rapid isothermal and isochronal annealings, there has been a significant increase in positive oxide-charge density and in oxide-breakdown time. A correlation between the density of the positive oxide charge and the oxide breakdown reliability has been established. We proposed that the improvement in the oxide-breakdown reliability, tested at electric field of 11 MV/cm, is attributed to trapping of injected electron by the positive oxide charge and not solely due to reduction of SiC-SiO₂ interface-trap density.     

Diffusional creep induced stress relaxation in thin Cu films on silicon

The results of stress measurements during annealing of thin copper films deposited on 100 μm Si substrates are presented. The stress in thin films was determined by using an optical system for curvature measurements. The annealing experiments were done during thermal cycles of heating and cooling procedures from room temperature up to 400 °C with a rate 10 °C/min. The total thickness of thin films was between 20 and 100 nm. The obtained results showed that the difference between the end and the initial values of the ratio of force to width increases with the thickness of the samples. The initial linear shape of the temperature-stress plots reaches higher temperature values with an increase in film thickness. In order to explain the observations, the dependence of stress on temperature was calculated using the rate of Coble creep. It was found that the theoretical curves reveal the same features as the experimental data. It was concluded that diffusional creep mechanism dominates for thin film of thickness below 100 nm.     

GISAXS analysis of Ge nanoparticles embedded ZnO thin films: The effect of oxygen partial pressure and thermal process on the nanostructured aggregations

Ge nanoparticles embedded in ZnO thin films (synthesized on p-type Si substrates) were investigated to explore their potential usage possibilities as diodes for opto-electronic devices and photovoltaics, thin-film transistors, and solar cells. Nano scale structural details under the effect of different gas pressure of O₂ may include some hints to understand and develop structure-property correlations of the focused type materials. With this purpose, GISAXS (Grazing-incidence small-angle X–ray scattering) was used for 3D structural analysis of the films according to the thermal process (Rapid Thermal Annealing: RTA and Absence of Thermal Effect: AS-MADE) and O₂ partial pressure during the deposition of ZnO matrix.As a result of the study, it may be said that size and shape controlled growth processes are possible for these types of films. Especially, increase in pressure indicates orthogonal like prismatic morphology at 1 mTorr, cylindrical at 3 mTorr and more compact spherical formation at 5 mTorr. That way, morphology controlled nanoscale growth can be achieved by changing the oxygen partial pressure for the oxide matrices. On the other hand, size of the nano aggregations decreases with increased partial pressure for both of RTA processed and AS-MADE samples. Decreasing ratio in the size of AS-MADE sample is bigger than that of RTA samples.     

Effects of substrate temperature on electrical and structural properties of copper thin films

This paper addresses the effects of substrate temperature on electrical and structural properties of dc magnetron sputter-deposited copper (Cu) thin films on p-type silicon. Copper films of 80 and 500 nm were deposited from Cu target in argon ambient gas pressure of 3.6 mTorr at different substrate temperatures ranging from room temperature to 250 °C. The electrical and structural properties of the Cu films were investigated by four-point probe and atomic force microscopy. Results from our experiment show that the increase in substrate temperature generally promotes the grain growth of the Cu films of both thicknesses. The RMS roughness as well as the lateral feature size increase with the substrate temperature, which is associated with the increase in the grain size. On the other hand, the resistivity for 80 nm Cu film decreases to less than 5 μΩ-cm at the substrate temperature of 100 °C, and further increase in the substrate temperature has not significantly decreased the film resistivity. For the 500 nm Cu films, the increase in the grain size with the substrate temperature does not conform to the film resistivity for these Cu films, which show no significant change over the substrate temperature range. Possible mechanisms of substrate-temperature-dependent microstructure formation of these Cu films are discussed in this paper, which explain the interrelationship of grain growth and film resistivity with elevated substrate temperature.     

液相过程制备的CdTe/Al 肖特基纳米晶太阳电池对烧结温度的依赖性研究

本文研究了烧结温度对液相过程制备的碲化镉(CdTe) 纳米晶薄膜性质的影响,以得到最优性能的CdTe/Al 肖特基纳米晶太阳电池。在AM 1.5 条件下,由350℃ 烧结的CdTe 薄膜制作太阳电池得到了2.67% 的最高效率。 当烧结温度增加到350℃ 时,薄膜中纳米晶尺寸明显增加。烧结温度在200℃ 到400℃ 范围内时,短路电流随温度增加而不断增加,但是,过度的烧结 (450℃) 处理会引起太阳电池的短路。     

硅中离子注入RTA剩余损伤对p－n结反向漏电流的影响

采用静电计测量了ＢＦ￣＋２、Ｆ￣＋Ｂ￣＋和Ａｒ￣＋＋Ｂ￣＋注入硅ＲＴＡ二极管的反向漏电流；借助高压透射电镜观察了ＢＦ￣＋２、Ｆ￣＋＋Ｂ“和Ａｒ￣＋＋Ｂ￣＋注入硅ＲＴＡ剩余损伤；深入讨论了剩余损伤对二极管反向漏电流的影响。结果表明，１）ＢＦ￣＋２注入二极管的反向漏电流最小，２）注入层剩余损伤和ＲＴＡ期间导致的热应力可能是影响二极管反向漏电流的主要原因。     

Effect of annealing temperature on structural,electrical and optical properties of spray pyrolytic nanocrystalline CdO thin films

Nanocrystalline CdO thin films were prepared onto a glass substrate at substrate temperature of 300 °C by a spray pyrolysis technique. Grown films were annealed at 250, 350, 450 and 550 °C for 2.5 h and studied by the X-ray diffraction, Hall voltage measurement, UV-spectroscopy, and scanning electron microscope. The X-ray diffraction study confirms the cubic structure of as-deposited and annealed films. The grain size increases whereas the dislocation density decreases with increasing annealing temperature. The Hall measurement confirms that CdO is an n-type semiconductor. The carrier density and mobility increase with increasing annealing temperature up to 450 °C. The temperature dependent dc resistivity of as-deposited film shows metallic behavior from room temperature to 370 K after which it is semiconducting in nature. The metallic behavior completely washed out by annealing the samples at different temperatures. Optical transmittance and band gap energy of the films are found to decrease with increasing annealing temperature and the highest transmittance is found in near infrared region. The refractive index and optical conductivity of the CdO thin films enhanced by annealing. Scanning electron microscopy confirms formation of nano-structured CdO thin films with clear grain boundary.