Diffusion barrier performance of Zr–N/Zr bilayered film in Cu/Si contact system

Zr–N/Zr bilayered film as a diffusion barrier between Cu and Si is evaluated. The thermal stability of the diffusion barrier is investigated by annealing the Cu/Zr–N/Zr/Si samples in N₂ for an hour. XRD, SEM and AES results for the above contact systems after annealing at 700 °C show that Cu film has preferential (1 1 1) crystal orientation and no diffraction peaks of Cu₃Si and a Cu–Zr–Si ternary compound are observed for all Cu/Zr–N/Zr/Si contact systems. In addition, the atomic distribution of Zr and Si is evident and grows with increasing temperature up to 700 °C, which corresponds to the Zr–Si phase having low contact resistivity. Low contact resistivity and high thermal stability diffusion barrier can be expected by the application of the Zr–N/Zr bilayered film as a diffusion barrier between Cu and Si.     

Study of diffusion barrier properties of ionized metal plasma (IMP) deposited TaN between Cu and SiO2

The diffusion barrier properties of IMP deposited TaN between Cu and SiO₂ have been investigated in the Cu (200 nm)/TaN (30 nm)/SiO₂ (250 nm)/Si multi-layer structure. The IMP-TaN thin film shows better Cu diffusion barrier properties than chemical vapor deposition (CVD) and conventional physical vapor deposition (PVD) deposited TaN films. The thermal stability was evaluated by electrical measurement and X-ray diffraction (XRD) analysis. As a main part of thermal stability studies, the atomic intermixing, new compound formation and phase transitions in the test structure were also studied. Furthermore, a failure mechanism was also examined by X-ray diffraction (XRD), scanning electron microscopy (SEM), atomic force microscopy (AFM), secondary ion mass spectroscopy (SIMS) and Rutherford backscattering spectroscopy (RBS) in conjunction with electrical measurements. The 30 nm thick IMP-TaN was found to be stable up to 800°C for 35 min.     

Integrity of copper–hafnium,hafnium nitride and multilayered amorphous-like hafnium nitride metallization under various thickness

The barrier properties and failure mechanism of sputtered Hf, HfN and multilayered HfN/HfN thin films were studied for the application as a Cu diffusion barrier in metallization schemes. The barrier capability and thermal stability of Hf, HfN and HfN/HfN films were determined using X-ray diffraction (XRD), leakage current density, sheet resistance (R_s) and cross-sectional transmission electron microscopy (XTEM). The thin multi-amorphous-like HfN thin film (10 nm) possesses the best barrier capability than Hf (50 nm) and amorphous-like HfN (50 nm). Nitrogen incorporated Hf films possess better barrier performance than sputtered Hf films. The Cu/Hf/n⁺–p junction diodes with the Hf barrier of 50 nm thickness were able to sustain a 30-min thermal annealing at temperature up to 500 °C. Copper silicide forms after annealing. The Hf barrier fails due to the reaction of Cu and the Hf barrier, in which Cu atoms penetrate into the Si substrate after annealing at high temperature. The thermal stabilities of Cu/Hf/n⁺–p junction diodes are enhanced by nitrogen incorporation. Nitrogen incorporated Hf (HfN, 50 nm) diffusion barriers retained the integrity of junction diodes up to 550 °C with lower leakage current densities. Multilayered amorphous-like HfN (10 nm) barriers also retained the integrity of junction diodes up to 550 °C even if the thickness is thin. No copper–hafnium and copper silicide compounds are found. Nitrogen incorporated hafnium diffusion barrier can suppress the formation of copper–hafnium compounds and copper penetration, and thus improve the thermal stability of barrier layer. Diffusion resistance of nitrogen-incorporated Hf barrier is more effective. In all characterization techniques, nitrogen in the film, inducing the microstructure variation appears to play an important role in thermal stability and resistance against Cu diffusion. Amorphousization effects of nitrogen variation are believed to be capable of lengthening grain structures to alleviate Cu diffusion effectively. In addition, a thin multilayered amorphous-like HfN film not only has lengthening grain structures to alleviate Cu diffusion, but block and discontinue fast diffusion paths as well. Hence, a thin multilayered amorphous-like HfN/HfN barrier shows the excellent barrier property to suppress the formation of high resistance η′-(Cu,Si) compound phase to 700 °C.     

Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing

2000 Å-SiO₂/Si(1 0 0) and 560 Å-Si₃N₄/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of ∼450°C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO₂∥Si₃N₄ wafer pair reached 2500 mJ/m², which was attained only above 1000°C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO₂ and Si₃N₄ films (Si/SiO₂∥Si₃N₄/Si) compared to the conventional method.     

High thermal annealing effect on structural and optical properties of ZnO–SiO2 nanocomposite

The effect of annealing temperature on photoluminescence (PL) of ZnO–SiO₂ nanocomposite was investigated. The ZnO–SiO₂ nanocomposite was annealed at different temperatures from 600 °C to 1000 °C with a step of 100 °C. High Resolution Transmission Electron Microscope (HR-TEM) pictures showed ZnO nanoparticles of 5 nm are capped with amorphous SiO₂ matrix. Field Emission Scanning Electron Microscope (FE-SEM) pictures showed that samples exhibit spherical morphology up to 800 °C and dumbbell morphology above 800 °C. The absorption spectrum of ZnO–SiO₂ nanocomposite suffers a blue-shift from 369 nm to 365 nm with increase of temperature from 800 °C to 1000 °C. The PL spectrum of ZnO–SiO₂ nanocomposite exhibited an UV emission positioned at 396 nm. The UV emission intensity increased as the temperature increased from 600 °C to 700 °C and then decreased for samples annealed at and above 800^°C. The XRD results showed that formation of willemite phase starts at 800 °C and pure willemite phase formed at 1000 °C. The decrease of the intensity of 396 nm emission peak at 900 °C and 1000 °C is due to the collapse of the ZnO hexagonal structure. This is due to the dominant diffusion of Zn into SiO₂ at these temperatures. At 1000 °C, an emission peak at 388 nm is observed in addition to UV emission of ZnO at 396 nm and is believed to be originated from the willemite.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.     

Power cycle reliability of Cu nanoparticle joints with mismatched coefficients of thermal expansion

The power cycle reliability of Cu nanoparticle joints between Al₂O₃ heater chips and different heat sinks (Cu-40 wt.%Mo, Al-45 wt.%SiC and pure Cu) was studied to explore the effect of varying the mismatch in the coefficient of thermal expansion (CTE) between the heater chip and the heat sink from 4.9 to 10.3 ppm/K. These joints were prepared under a hydrogen atmosphere by thermal treatment at 250, 300 and 350 °C using a pressure of 1 MPa, and all remained intact after 3000 cycles of 65/200 °C and 65/250 °C when the CTE mismatch was less than 7.3 ppm/K, despite vertical cracks forming in the sintered Cu. When the CTE mismatch was 10.3 ppm/K, the Cu nanoparticle joint created at 300 °C endured the power cycle tests, but the joint created at 250 °C broke by lateral cracks in the sintered Cu after 1000 cycles of 65/200 °C. The Cu nanoparticle joint created at 350 °C also broke by vertical cracks in the heater chip after 1000 cycles of 65/250 °C, suggesting that although sintered Cu can be strengthened to tolerate the stress by increasing the joint temperature, this eventually causes the weak and brittle chip to fracture through accumulated stress. The calculation results of stresses on the heater chip showed that the stress can be higher than the strength of Al₂O₃ when the CTE mismatch is 10.3 ppm/K and the Young's modulus of the sintered Cu is higher than 20 GPa, suggesting that the heater chip can be broken.     

Reliability of Cu nanoparticle joint for high temperature power electronics

Power cycle reliability of Cu nanoparticle joint has been studied for high temperature operation of power devices. Al₂O₃ heater chips and Cu–65 wt% Mo baseplates were joined by Cu nanoparticles and Sn–0.7Cu and power cycle tests of 65/200 °C and 65/250 °C were carried out on the joints. The Cu nanoparticles were prepared by reducing Cu carbonate in ethylene glycol with dodecanoic acid + dodecyl amine (C12) and decanoic acid and decyl amine (C10) as capping agents. A power cycle test of 65/200 °C did not inflict severe damage on the Cu nanoparticle joints so that there were not many cracks formed after 3000 cycles. Vertical cracks were formed in the C12 Cu nanoparticle joint after 3000 cycles of 65/250 °C test, however the maximum temperature during the power cycle test did not change at all because vertical cracks did not have an effect on preventing heat flow. On the contrary, lateral cracks were completely formed in the Sn–0.7Cu soldered joint after 200 cycles of 65/200 °C test and in the C10 Cu nanoparticle joint after 360 cycles of 65/250 °C test. In these experiments, the maximum temperatures were rapidly increased because heat conduction was prevented across the formed lateral cracks.     

Elimination of impurities from the surface of silicon using hydrochloric and nitric acid

Acid leaching of silicon is insufficient in order to achieve solar grade silicon. Leaching of silicon previously purified by the copper gathering method can significantly reduce amount of impurities congregated in the Cu–Si intermetallic phase during solidification process. Two samples of 50 wt% Cu–50 wt% Si alloy were solidified at 0.5 and 1.0 °C/min cooling rate. They were treated with 10 vol% HNO₃ and 5 vol% HCl and 7 vol% HNO₃. The inductively Coupled Plasma Mass Spectrometry technique was employed to measure traces of impurities before and after the treatment. It was determined that the overall impurity level in purified silicon was reduced from 5277 ppm_wt to 225.5 ppm_wt. The samples cooled at 0.5 °C/min achieved lower impurities levels in all instances while the sample leached with 10% HNO₃ produced the greatest reduction in impurity level. Scanning electron microscopy and Energy Dispersive X-Ray Spectroscopy analysis showed that the traces of Cu–Si intermetallic together with gathered impurities can be found only in the large silicon particles after the acid leaching treatment. In all instances, the surface of the silicon particles was free of impurities while Si yield was preserved at above 97%.     

Design,development and reliability testing of a low power bridge-type micromachined hotplate

In this paper, the development and reliability of a platinum-based microheater with low power consumption are demonstrated. The microheater is fabricated on a thin SiO₂ bridge-type suspended membrane supported by four arms. The structure consists of a 0.6 μm-thick SiO₂ membrane of size 50 μm × 50 μm over which a platinum resistor is laid out. The simulation of the structure was carried out using MEMS-CAD Tool COVENTORWARE. The platinum resistor of 31.0 Ω is fabricated on SiO₂ membrane using lift-off technique. The bulk micromachining technique is used to create the suspended SiO₂ membrane. The temperature coefficient of resistance (TCR) of platinum used for temperature estimation of the hotplate is measured and found to be 2.2 × 10⁻³/°C. The test results indicate that the microhotplate consumes only 11.8 mW when heated up to 400 °C. For reliability testing, the hotplate is continuously operated at higher temperatures. It was found that at 404 °C, 508 °C and 595 °C, the microhotplate continuously operated up to 16.5 h, 4.3 h and 4 min respectively without degrading its performance. It can sustain at least 53 cycles pulse-mode of operation at 540 °C with ultra-low resistance and temperature drifts. The structure has maximum current capability of 19.06 mA and it can also sustain the ultrasonic vibration at least for 30 min without any damage.     

Reliable impurity trap memory with high charge trap efficiency using ultrathin SiO2 impurity host layer for nonvolatile memory application

We demonstrated reliable impurity trap memory (ITM) with high charge trap efficiency by incorporating only 1 nm-SiO₂ impurity host layer (IHL) between Al₂O₃ diffusion barrier layer and blocking oxide. While the ITM without IHL showed significant retention degradation as the amount of Ti impurity increased from 0.7 to 3 Å for enlarging memory window, the ITM with IHL showed stable retention characteristic which is charge loss less than 1 V after 10⁴ s at 85 °C. We postulated that the chemical reaction between Ti and SiO₂ induced three dimensionally-distributed impurity traps in IHL, which could result in the well-discrete stored charges in program mode.     

Investigation of Si/SiGe/Si heterostructure implanted by H ion and annealed in vacuum and dry O2 ambient

The 20-nm-thick Si cap layer/74-nm-thick Si_0.72Ge_0.28 epilayer/Si heterostructures implanted by 25 keV H⁺ ion to a dose of 1×10¹⁶ cm⁻² were annealed in ultra-high vacuum ambient and dry O₂ ambient at the temperature of 800 °C for 30 min, respectively. Rutherford backscattering/ion channeling (RBS/C), Raman spectra, high-resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) were used to characterize the structural characteristics of the Si_0.72Ge_0.28 layer. Investigations by RBS/C demonstrated that the crystal quality of the Si/Si_0.72Ge_0.28/Si heterostructure sample implanted by 25 keV H⁺ in conjunction with subsequent annealing in dry O₂ ambient is superior to that of identical sample annealing in ultra-high vacuum ambient. The less strain relaxation of SiGe layer of the Si/Si_0.72Ge_0.28/Si heterostructures implanted by H ion and annealed in dry O₂ ambient at the temperature of 800 °C for 30 min could be doublechecked by Raman spectra as well as HRXRD, which was compared with that in an identical sample annealed in ultra-high vacuum ambient for identical thermal budget. In addition, the SiGe layer of the H-implanted Si/SiGe/Si heterostructural sample annealed in dry O₂ ambient accompanied by better crystal quality and less strain relaxation made its surface morphology superior to that of the sample annealed in ultra-high vacuum ambient at the temperature of 800 °C for 30 min, which was also verified by AFM images.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

Influences of post-annealing temperature on the structural and electrical properties of mixed oxides (CuFeO2 and CuFe2O4) thin films prepared by spray pyrolysis technique

P-type mixed oxides (CuFeO₂ and CuFe₂O₄) transparent conducting thin films have been successfully deposited on p-type Si (111) substrates at 450 °C by spray pyrolysis deposition (SPD) and annealed at 800 °C for 2 h. The crystal structure, surface morphology and electrical property have been investigated. It is observed that the CuFeO₂ and CuFe₂O₄ thin films as deposited and annealed, have polycrystalline hexagonal structure and the crystallite size increases by annealing processes. The electrical property of the Ni/CuFeO₂/Si Metal–Semiconductor–Metal (MSM) photo detectors was investigated using the current–voltage (I–V) measurements. The barrier heights ϕ_Β of Ni/CuFeO₂/Ni MSM thin films of as deposited and annealed on Si substrates were calculated and its values are 0.478, 0.345 eV, respectively with an applied bias voltage of 3 V.     

Comparison of WTi and WTi(N) as diffusion barriers for Al and Cu metallization on Si with respect to thermal stability and diffusion behavior of Ti

The thermal stability of WTi and WTi(N) as diffusion barriers for Al and Cu metallization on Si (1 0 0) was investigated by time of flight secondary ion mass spectrometry (ToF-SIMS) depth profiling, X-ray diffraction (XRD), electron microscopy (SEM and TEM) and X-ray photoelectron spectroscopy (XPS). For both, Al and Cu, Ti diffusion out of WTi into the metal was proved to occur at elevated temperatures (400 °C for Al and 600 °C for Cu) which further results in barrier film failure. Nitrogen incorporation into WTi leads to an elimination of the Ti diffusion and consequently to a better thermal stability of the barrier film. It is shown that besides crystal structure, Ti diffusion into the metallization is an essential factor of the barrier failure mechanism. The failure temperature for Al is lower than for Cu.     

Effects of RTA temperatures on conductivity and micro-structures of boron-doped silicon nanocrystals in Si-rich oxide thin films

In this work, the B-doped Si rich oxide (SRO) thin films were deposited and then annealed using rapid thermal annealing (RTA) to form SiO₂-matrix silicon nanocrystals (Si NCs). The effects of the RTA temperatures on the structural properties, conduction mechanisms and electrical properties of B-doped SRO thin films (BSF) were investigated systematically using Hall measurements, Fourier transform infrared spectroscopy and Raman spectroscopy. Results showed that the crystalline fraction of annealed BSF increased from 41.3% to 62.8%, the conductivity was increased from 4.48×10⁻³ S/cm to 0.16 s/cm, the carrier concentration was increased from 8.74×10¹⁷ cm⁻³ to 4.9×10¹⁸ cm⁻³ and the carrier mobility was increased from 0.032 cm² V⁻¹ s⁻¹ to 0.2 cm² V⁻¹ s⁻¹ when the RTA temperatures increased from 1050 °C to 1150 °C. In addition, the fluctuation induced tunneling (FIT) theory was applicable to the conduction mechanisms of SiO₂-matrix boron-doped Si-NC thin films.     

Young's modulus of a sintered Cu joint and its influence on thermal stress

Al₂O₃ chips and pure Cu plates were joined by Cu nanoparticles at 250 °C and 350 °C, and the Young's moduli of the sintered Cu were evaluated by nanoindentation tests. The average Young's moduli were 52.7 ± 19.8 GPa and 76.5 ± 29.7 GPa at 250 °C and 350 °C, respectively, indicating that the sintered structures were strengthened at higher temperatures. The calculation results indicated that the joint at 350 °C has a high Young's modulus, but make the stress higher than the chip strength, resulting in breakage of the chip during 65/250 °C power cycling.     

Enhancement in electrical performance of indium gallium zinc oxide-based thin film transistors by low temperature thermal annealing

We have studied the characteristics of transparent bottom-gate thin film transistors (TFTs) using In–Ga–Zn–O (IGZO) as an active channel material. IGZO films were deposited on SiO₂/Si substrates by DC sputtering techniques. Thereafter, the bottom-gate TFT devices were fabricated by depositing Ti/Au metal pads on IGZO films, where the channel length and width were defined to be 200 and 1000 μm, respectively. Post-metallization thermal annealing of the devices was carried out at 260, 280 and 300 °C in nitrogen ambient for 1 h. The devices annealed at 280 °C have shown better characteristics with enhanced field-effect mobility and high on–off current ratio. The compositional variation of IGZO films was also observed with different annealing temperatures.     

Effect of the film thickness on the crystal structure and ferroelectric properties of (Hf0.5Zr0.5)O2 thin films deposited on various substrates

In this work, the effect of the film thickness on the crystal structure and ferroelectric properties of (Hf_0.5Zr_0.5)O₂ thin films was investigated. The thin films were deposited on (111) Pt-coated SiO₂, Si, and CaF₂ substrates with thermal expansion coefficients of 0.47, 4.5, and 22×10⁻⁶/°C, respectively. From the X-ray diffraction measurements, it was found that the (Hf_0.5Zr_0.5)O₂ thin films deposited on the SiO₂ and CaF₂ substrates experienced in-plane tensile and compressive strains, respectively, in comparison with the films deposited on the Si substrates. For films deposited on all three substrates, the volume fraction of the monoclinic phase increased with increasing film thickness, with the SiO₂ substrate having the lowest monoclinic phase volume fraction at all film thicknesses tested. The grain size of the films, which is an important factor for the formation of the ferroelectric phase, remained almost constant at about 10 nm in diameter regardless of the film thickness and type of substrate utilized. Ferroelectricity was observed for the 17 nm-thick films deposited on SiO₂ and Si substrates, and the maximum remanent polarization (P_r) value of 9.3 µC/cm² was obtained for films deposited on the SiO₂ substrate. In contrast, ferroelectricity with P_r=4.4 µC/cm² was observed only for film on SiO₂ substrate in case of 55 nm-thick films. These results suggest that the films under in-plane tensile strain results in the larger ferroelectricity for 17 nm-thick films and have a ferroelectricity up to 55 nm-thick films.