Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.     

A fast‐corrected all‐digital DCC with synchronous input clock

This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between ?2.4 and 2.7%. The largest static phase error between the input and output clock is ?44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm² and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd.     

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

An all‐digital DLL with duty‐cycle correction using reusable TDC

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide‐operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18‐µm complementary metal‐oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8‐V supply at 900 MHz. The peak‐to‐peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

Enhanced active‐feedback frequency compensation with on‐chip‐capacitor reduction feature for amplifiers with large capacitive load

A large capacitive load amplifier with enhanced active‐feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide‐bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130‐nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on‐chip resistor is needed; only a 0.91‐pF compensation capacitor is used to maintain stability. The achieved gain‐bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm². Copyright © 2017 John Wiley & Sons, Ltd.     

Towards analog implementations of PWL two‐dimensional non‐linear functions

This paper deals with the circuit implementation of non‐linear algebraic bivariate functions. The synthesis procedure is based on a piecewise‐linear approximation technique and on a corresponding circuit architecture, whose basic element is a circuit block with the input/output function y(x) = max(0; x). Some known CMOS circuit structures that can be used to obtain such a block are considered, and their main advantages and drawbacks are pointed out. The static and dynamic features of both the single circuit block and the overall architecture for two‐dimensional PWL functions are illustrated by way of examples. Copyright © 2005 John Wiley & Sons, Ltd.     

A single‐stage phase‐shifted full‐bridge AC/DC converter with variable frequency control

This letter presents a single‐stage soft‐switched full‐bridge AC/DC converter for low‐voltage/high‐current output applications. A phase‐shifted method with a variable frequency control is used to regulate the DC bus voltage and the output voltage of the single‐stage AC/DC converter. The proposed circuit topology and control scheme exhibit superior performances (i.e. high power factor, high‐efficiency, and ring‐free features). Correspondingly, a laboratory prototype, 500 W 5V/100A AC/DC converter, is implemented to verify the feasibility of the proposed design. Copyright © 2009 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

Limit‐cycle stable control of current‐mode dc‐dc converter with zero‐perturbation dynamical compensation

Regarding the non‐limit‐cycle instabilities, which commonly exist in the feedback‐controlled switching power converters, a new zero‐perturbation dynamical compensation method is proposed based on a simplified self‐stable dynamical compensation condition in this paper. With a current‐mode Buck converter as the subject of investigation, the corresponding self‐stable perturbation control equation is given. At the same time, the system stability boundary is obtained based on the investigation of the system eigenvalues, and hence, the working range of control parameters is determined. Finally, the presented simulation and experiment results reveal that the new zero‐perturbation dynamical compensation controller is easily realized with an analog circuit and it will not sacrifice the working range of the original reference current compared with the traditional slope compensation. Copyright © 2013 John Wiley & Sons, Ltd.     

A high-resolution all-digital pulse-width modulator architecture with a tunable delay element in CMOS

A design for an all-digital high-resolution pulse-width modulator (HRPWM) architecture is presented in this work. The architecture is based on a novel digitally controlled delay element that combines two different approaches, achieving a variable time interval up to 54 ps, and adjustable against process, voltage, and temperature (PVT) variations. The proposed system uses several delay elements with a counter-based digital pulse-width modulator (DPWM) in a hybrid configuration, which allows to obtain duty cycles with 18-bit resolution without using a high-frequency internal clock and maintaining a low power dissipation. The HRPWM was implemented in a standard low-cost 130-nm CMOS technology, together with a memory used to store the duty cycles, and a serial communication module. Post layout simulation results show good linearity between the control word and the duty cycle in all the range. The chip can be fine tuned to improve its performance using the calibration capabilities of the architecture. The analysis includes a comparison with another state-of-art HRPWMs showing the advantages of the proposed approach.     

A minute asymmetrical current injection based anti‐islanding method for three‐phase grid‐connected photovoltaic inverters

An active anti‐islanding protection method based on the current control for a three‐phase grid‐connected photovoltaic inverter is proposed in this paper. The current of phase‐a is synchronous with the corresponding phase voltage at the point of common coupling in its positive half cycle, and a zero‐current zone is inserted at the end of the cycle in a negative half cycle. As for phase‐c, the zero‐current zone is inserted in the positive half cycle of the current, and the current in a negative half cycle of phase‐c is in phase with the corresponding phase voltage. Therefore, the currents of phase‐a and phase‐c in one cycle become slightly asymmetrical. Before the islanding takes place, the positive and negative half cycles of three‐phase voltages are symmetrical due to the operation of the grid voltage. While islanding takes place, a time difference between the positive and negative half cycles of the voltages of phase‐a and phase‐c will be generated and the islanding is detected in accordance with the successive cycles fulfilling the conditions of islanding identification. In order to measure zero‐crossings of the voltages accurately, an finite impulse response filter is used to smooth out the voltage harmonics and noises. Simulations and experiments for three‐phase three‐wire power systems have been carried out. The results verify that the proposed method can detect the islanding for a parallel RLC load or induction motors when the voltage frequency is within the range of the non‐detection zone. It is seen from the analysis of the detecting principle that there is no influence of temporal voltage frequency fluctuation on the proposed method even if a large load connected to a weak power system frequently starts up or stops. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Synthesis of multiport resistors with piecewise‐linear characteristics: a mixed‐signal architecture

Non‐linear multiport resistors are the main ingredients in the synthesis of non‐linear circuits. Recently, a particular PWL representation has been proposed as a generic design platform (IEEE Trans. Circuits Syst.‐I 2002; 49 :1138–1149). In this paper, we present a mixed‐signal circuit architecture, based on standard modules, that allows the electronic integration of non‐linear multiport resistors using the mentioned PWL structure. The proposed architecture is fully programmable so that the unit can implement any user‐defined non‐linearity. Moreover, it is modular: an increment in the number of input variables can be accommodated through the addition of an equal number of input modules. Copyright © 2005 John Wiley & Sons, Ltd.     

Energy‐efficient single‐clock‐cycle binary comparator

A new fast low‐power single‐clock‐cycle binary comparator is presented. High speed is assured by using parallel‐prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

Multistage multiphase switched‐capacitor DC–DC converter with variable‐phase and PWM control

A closed‐loop multistage multiphase switched‐capacitor converter (n‐stage p‐phase MPSC) is proposed with a variable‐phase control (VPC) and a pulse‐width‐modulation (PWM) technique for low‐power step‐up conversion and high‐efficiency regulation. In this n‐stage MPSC, n voltage doublers are connected in series for boosting the voltage gain up to 2ⁿ at most. Here, VPC is suggested to realize a variable multiphase operation by changing the phase number p and topological path for the more suitable level of voltage gain so as to improve the power efficiency, especially for the lower output voltage Besides, PWM is adopted not only to enhance output regulation for different desired outputs, but also to reinforce output robustness to source/loading variation. Further, some theoretical analyses and designs include: n‐stage p‐phase MPSC model, steady‐state analysis, conversion ratio, power efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed‐loop MPSC is simulated, and the hardware is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Design of a two‐output forward converter with an output voltage objective function

A new method is proposed in this paper to distribute the steady‐state output voltage errors in a two‐output forward converter. The cross regulation between the two output voltages are described in terms of the circuit parameters. An objective function is formed for each of the two outputs to track its reference within the specified error. The legitimate duty cycle range is located through the transfer characteristics between the duty cycle and the load currents. The weighting feedback gains of the two output voltages can be determined by the presented control scheme which optimizes the objective function. The proposed method is suitable for a two‐output system without a dominant load. Experiments on a prototype are conducted to show that there exist a duty cycle range and a set of weighted feedback gains minimizing the defined objective function. Copyright © 2010 John Wiley & Sons, Ltd.     

A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

Non‐isolated single‐switch DC–DC converters with extended duty cycle for high step‐down voltage applications

Several new topologies of single‐switch non‐isolated DC–DC converters with wide conversion gain and reduced semiconductor voltage stress are proposed in this paper. Most of the proposed topologies are derived from the conventional inverse of SEPIC (Zeta) converter. The proposed topologies can operate with larger switch duty cycles compared with the existing single switch topologies, hence, making them well suitable for high step‐down voltage conversion applications. With extended duty cycle, the current stress in the active power switch is reduced, leading to a significant improvement of the system losses. Moreover, the active power switch in some of the proposed topologies is utilized much better compared to the conventional Zeta and quadratic‐buck converters. The principle of operation, theoretical analysis, and comparison of circuit performances with other step‐down converters are discussed regarding voltage and current stress and switch silicon utilization. Finally, simulation and experimental results for a design example of a 50 W/5 V at 42‐V input voltage operating at 50 kHz will be provided to evaluate the performance of the proposed converters. Copyright © 2014 John Wiley & Sons, Ltd.