A low‐power four‐stage amplifier for driving large capacitive loads

A four‐stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole‐zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain‐bandwidth product of 18 MHz consuming only 40.9 μW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain‐bandwidth product and dissipates 55.2 μW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.     

Wireless power charger for wearable medical devices with in‐band communication

A wireless power charger integrated circuit has been developed for wearable medical devices in a 0.18‐µm Bipolar, Complementary metal‐oxide‐semiconductor, and Lightly‐Doped Metal‐Oxide‐Semiconductor (BCDMOS) process. A passive full‐wave rectifier consisting of Schottky diodes and cross‐coupled n‐type Metal‐Oxide‐Semiconductor (nMOS) transistors performs the alternating current to direct current power conversion without any reverse leakage current. To charge a battery, a linear charger circuit follows the passive rectifier instead of a switching charger circuit for the small form factor of wearable medical devices. An in‐band communication circuit notifies the proper connection of the wireless power receiver and the battery charging status to the charging pad (wireless power transmitter) through the wireless power transmission channel. The wireless power charger integrated circuit occupies 1.44‐mm² silicon area and shows 31.7% power efficiency when the charging current is 26.6 mA. Copyright © 2015 John Wiley & Sons, Ltd.     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel single‐stage AC–DC converter with quasi‐resonant zero‐voltage‐switching for high power factor and high efficient applications

A new single‐stage‐isolated ac–dc converter that can guarantee both high efficiency and high power factor is proposed. It is based on a new dc–dc topology that has prominent conversion ratio similar to that of boost topology so that it is adequate to deal with the universal ac input. In addition, since it utilizes the transformer more than others based on the general flyback topology, the size of whole power system can be reduced due to the reduced transformer. Moreover, the voltage stresses on the secondary rectifiers can be clamped to the output voltage by adopting the capacitive output filter and clamp diode, and the turn‐off loss in the main switch can be reduced by utilizing the resonance. Furthermore, since this converter operates at the boundary conduction mode, the line input current can be shaped as the waveform of a line voltage automatically and the quasi‐resonant zero‐voltage switching can be obtained. Consequently, it features higher efficiency, lower voltage stress, and smaller sized transformer than other topologies. A 100 W prototype has been built and tested as the validation of the proposed topology. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

A single‐stage high power‐factor bridgeless AC‐LED driver for lighting applications

An alternating‐current light‐emitting diode (AC‐LED) driver is implemented between the grid and lamp to eliminate the disadvantages of a directly grid‐tied AC‐LED lamp. In order to highlight the benefits of AC‐LED technology, a single‐stage converter with few components is adopted. A high power‐factor single‐stage bridgeless AC/AC converter is proposed with higher efficiency, greater power factor, less harmonics to pass IEC 61000‐3‐2 class C, and better regulation of output current. The brightness and flicker frequency issues caused by a low‐frequency sinusoidal input are surpassed by the implementation of a high‐frequency square‐wave output current. In addition, the characteristics of the proposed circuit are discussed and analyzed in order to design the AC‐LED driver. Finally, some simulation and experimental results are shown to verify this proposed scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

A waveform generator circuit for extra low‐frequency CMOS micro‐power applications

This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.     

A battery charger with maximum power point tracking function for low‐power photovoltaic system applications

A battery charger with MPPT function for low‐power PV system applications is presented in this study. For effective miniaturization, the battery charger is designed with high‐frequency operation. Some current‐sensing techniques are studied, and their MPPT implementation is compared. A battery charging method is also designed to prolong battery lifetime without the use of battery current sensors. The operation principles and design considerations of the proposed PV charger are analyzed and discussed in detail. A laboratory prototype is implemented and tested to verify the feasibility of the proposed scheme. Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high‐frequency operation. Copyright © 2010 John Wiley & Sons, Ltd.     

A matrix‐exponential decomposition‐based time‐domain method for band structure calculation of one‐dimensional periodic structures

A time‐domain method for calculating the band structure of one‐dimensional periodic structures is proposed. During the time‐stepping of the method, the column vector containing the spatially sampled field data is updated by multiplying with an iteration matrix. The iteration matrix is first obtained by using the matrix‐exponential decomposition technique. Then, the small nonzero elements of the matrix are pruned to improve its sparse structure, so that the efficiency of the matrix–vector multiplication involved in each time‐step is enhanced. The numerical results show that the method is conditionally stable but is much more stable than the conventional finite‐difference time‐domain (FDTD) method. The time‐step with which the method runs stably can be much larger than the Courant–Friedrichs–Lewy (CFL) limit. And moreover, the method is found to be particularly efficient for the band structure calculation of large‐scale structures containing a defect with a very high wave speed, where the conventional FDTD method may generally lose its efficiency severely. For this kind of structures, not only the stability requirement can be significantly relaxed, but also the matrix‐pruning operation can be very effectively performed. In the numerical experiments for large‐scale quasi‐periodic phononic crystal structures containing a defect layer, significantly higher efficiency than the conventional FDTD method can be achieved by the proposed method without an evident accuracy deterioration if the wave speed of the defect layer is relatively high. Copyright © 2016 John Wiley & Sons, Ltd.     

A model‐based dead‐band compensation for the dual‐active‐bridge isolated bidirectional DC–DC converter

The dual active bridge (DAB)‐based isolated bidirectional converter has been used to realize bidirectional energy flow while offering needed isolation between the primary and secondary side: for example, the battery side and grid side of one plug‐in hybrid electric vehicle (PHEV). Even though the operation of a DAB‐based DC–DC converter is straightforward, various transient processes exist, such as the dead‐band effect, which deeply affects the dynamic performance of the converter in real world applications. Compensation of this effect is not easy because of the strong nonlinearity of the entire system. This paper quantitatively analyzed the dead‐band effect at different output powers, and presented a model‐based controller to realize the nonlinear dead‐band compensation strategy, which can effectively mitigate demerits of the traditional PI‐based control strategy. The proposed control algorithm is validated through theoretical simulation and experimental results. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A low‐power small‐area 10‐bit analog‐to‐digital converter for neural recording applications

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog‐to‐digital converters (ADCs). A time‐based approach is used for the subtraction and amplification in conjunction with a current‐mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog‐to‐digital conversion. Based on introduced structure, a 10‐bit 100‐kSample/s time‐based cyclical ADC has been designed and simulated in a standard 90‐nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system‐level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal‐to‐noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of ?64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280µm × 250µm. The total power dissipation is 5µW per conversion stage and 20µW from an 1.2‐V supply for full‐scale conversion. Copyright © 2010 John Wiley & Sons, Ltd.     

Double resonant tank LLC‐DCX based two‐stage power supply for magnetic levitation control system applications

Magnetic levitation train power supply systems, or Maglev, are most commonly powered by 330‐V high‐voltage direct current power systems. The power supply for maglev control system is used to provide a stable voltage to the suspension control circuit, which is the key part of Maglev trains. The suspension control power supply is typically a DC–DC converter with a high voltage input and multiple low voltage outputs. The traditional solutions typically lead to the following issues, such as uncontrolled duty ratio, poor cross‐regulation capability, and low reliability. In order to solve these problems, a novel two‐stage solution employing a double resonant tank LLC DC transformer (LLC‐DCX) is proposed and developed in this paper. The proposed solution not only increases the overall conversion efficiency significantly because of the achieved soft‐switching over the entire operation range, but also realizes the low input current ripple and high reliability owing to a uniform thermal distribution. A 210‐W, 220–380‐V input laboratory prototype with four outputs is fabricated and tested, and the experimental results are presented in this paper. The declared features of the proposed solution are well demonstrated by the experimental results. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A low‐loss high‐power single‐pole 8‐throw antenna switch adopting body self‐adapting bias technique in a 0.18‐μm thick‐film partially depleted silicon‐on‐insulator complementary metal‐oxide‐semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body‐contacted field‐effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body‐contacted field‐effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self‐adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon‐on‐insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1‐dB compression point (P_?0.1dB), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P_?0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.     

A single‐stage integrated bridgeless AC/DC converter for electrolytic capacitor‐less LED lighting applications

In this paper, a single‐stage integrated bridgeless AC/DC converter is proposed. As compared to its counterpart that is composed of totem‐pole boost power factor correction (PFC) cascade fly‐back DC/DC converter, the studied circuit has less components number while overcoming the limits of the totem‐pole type. Thus, it is suitable to the low‐power LED lighting applications. Furthermore, when both PFC inductors L_b and magmatic inductance L_m of the transformer TR1 operate at discontinuous current mode, the bus voltage v_CB can be used to decouple the ac input and constant dc output power. Thus, the approach of increasing bus voltage ripple is employed to eliminate electrolytic capacitors and obtain long operation lifetime. Additionally, it is able to be compatible with our studied twin‐bus configuration for increasing the overall efficiency. A 50‐W hardware prototype has been designed, fabricated, and tested in the laboratory to verify the proposed converter validity. Copyright © 2014 John Wiley & Sons, Ltd.     

A useful identification method to build low‐order transfer function models based on frequency response for small‐signal stability analysis

This paper presents a scheme of small‐signal stability analysis for very large radial power systems. Generally, a radial power system can be easily classified as one main system and some external systems. Therefore, if accurate low‐order model of the external systems could be identified, the analysis effort for small‐signal stability can be reduced. Some dynamic reduction methods are proposed. Especially, the frequency‐domain least‐squares approximation methods, which are powerful and have high numerical reliability. This paper proposes a modal rebuild logic to improve the result obtained by the frequency‐domain least‐squares approximation methods. The proposed method provides high accuracy and a practical low‐order transfer function model. This paper introduces the usefulness of the proposed method with some numerical examples. In addition, merging sophisticated data handling and advanced applications in order to reduce human efforts is also discussed. This paper mentions the importance of automated node ID handling in order to realize the classification of system data into some partial data sets. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Fault detection for a class of network‐based nonlinear systems with communication constraints and random packet dropouts

This paper is dealt with the fault detection (FD) problem for a class of network‐based nonlinear systems with communication constraints and random packet dropouts. The plant is described by a Takagi–Sugeno fuzzy time‐delay model, it has multiple sensors and only one of them is actually communicated with the FD filter at each transmission instant, and the packet dropouts occur randomly. The goal is to design a FD filter such that, for all unknown inputs, control inputs, time delays and incomplete data conditions, the estimation error between the residual and ‘fault’ (or, more generally, the weighted fault) is minimized. By casting the addressed FD problem into an auxiliary H_∞ filtering problem of a stochastic switched fuzzy time‐delay system, a sufficient condition for the existence of the desired FD filter is established in terms of linear matrix inequalities. A numerical example is provided to illustrate the effectiveness and applicability of the proposed technique. Copyright © 2011 John Wiley & Sons, Ltd.