Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

A symmetric quantum-dot cellular automata design for 5-input majority gate

By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.     

Massively parallel systolic‐array architectures for 2d IIR polyphase space–time plane‐wave beam digital filters

A systolic architecture has recently been proposed for implementing two‐dimensional infinite impulse response (IIR) space–time beam plane‐wave filters at a throughput of one‐frame‐per‐clock–cycle for such applications as real‐time broadband smart antennas. A novel polyphase systolic architecture is proposed here that further increases the throughput of these IIR beam filters, by a factor of M, to M‐frames‐per‐clock‐cycle, where M is the number of polyphases. The proposed method combines the polyphase approach, along with pipelining and look‐ahead optimization methods, to achieve frame sample frequencies that are several times higher than the clock‐cycle limit of the very large‐scale integration (VLSI) technology, thereby potentially allowing multi‐GHz frame sample frequencies using current custom VLSI circuits. The implementation of a field programmable gate array‐based real‐time prototype is described, tested and verified for the two‐phase case (M = 2) at a technology‐limited clock frequency of 50 MHz which corresponds to a throughput of 100 million‐frames‐per‐clock–cycle. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of \(0.02\,\upmu \hbox {m}^{2}\) and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.     

A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel efficiency‐enhancement topology: GaN high‐electron mobility transistors with waveform‐modulation structure composed of Schottky diodes

To improve the power‐added efficiency (PAE) of the gallium nitride (GaN) high‐electron mobility transistor (HEMT) in radio frequency applications, this paper studies the relationship between the nonlinearity of the gate capacitance and the PAE of the GaN HEMTs. The theoretical analysis and simulation results demonstrate that the nonlinearity of the gate capacitance modulates the signal phase at the GaN HEMT input and increases the average drain current, leading to increased power consumption and reduced PAE. Then, an efficiency‐enhancement topology for GaN HEMTs that employs the waveform‐modulation effect of Schottky diodes to reduce power consumption and improve efficiency is presented. The efficiency‐enhancement topology for a 4 × 100‐μm GaN HEMT with waveform‐modulation diodes is then fabricated. Results of load‐pull test demonstrate that the novel topology can increase the PAE of the 4 × 100‐μm GaN HEMT by more than 5% at 8 GHz. The novel efficiency‐enhancement topology for GaN HEMTs proposed in this paper will be suitable for applications that demand high‐efficiency GaN HEMTs or circuits.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

Novel current‐source multilevel inverter driven by single gate drive power supply

This paper proposes a novel current‐source multilevel inverter, which is based on a current‐source half‐bridge topology. Multilevel inverters are effective for reducing harmonic distortion in the output voltage and the output current. However, the multilevel inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but the pulse width of the output PWM waveform is limited. Furthermore, high‐speed power switching devices are indispensable to create a high‐frequency power converter, but various problems, such as high‐frequency noise, arise due to the high dv/dt rate, especially in high‐side switching devices. The proposed current‐source multilevel inverter is composed of a common emitter topology for all switching devices. Therefore, it is possible to operate it with a single power supply for the gate drive circuit, which allows stabilizing the potential level of all the drive circuits. In this paper, the effectiveness of the proposed circuit is verified through experimental results. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(2): 88–95, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20475     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

A self‐calibrated delay‐locked loop with low static phase error

In conventional delay‐locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D‐type flip flop. The setup time of D‐type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 µm CMOS process design, with a reference frequency of 700 ~ 900 MHz. The active area is 0.031 mm², and the phase error after correction is less than 5 ps. Copyright © 2015 John Wiley & Sons, Ltd.     

Newly proposed hybrid resonant commutation bridge‐leg link snubber‐assisted three‐phase ZVZCS‐PWM soft‐switching inverter

This paper presents the newly proposed hybrid resonant commutation bridge‐leg link (HRCB) snubber circuit which can achieve zero voltage and zero current soft‐switching commutation for single‐phase and three‐phase voltage source‐type inverter, along with its unique features and operation principle. The circuit parameter design approach for the HRCB snubber circuit and the determination estimating scheme of the gate pulse timing processing which is more suitable and acceptable for single‐phase and space voltage vector modulated three‐phase voltage source inverter using the HRCB snubber circuit are described in this paper. In particular, the three‐phase voltage source soft‐switching inverter associated with the proposed HRCB circuits are evaluated and discussed from simulation and experimental viewpoints. The practical effectiveness of the HRCB snubber‐assisted three‐phase voltage source soft‐switching inverter using IGBT power modules which is based on the instantaneous space voltage vector modulation is clarified on the output voltage waveform, actual efficiency of electromagnetic noise in comparison with three‐phase voltage source‐type conventional hard‐switching inverter. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(4): 75–84, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20111     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

A fast‐corrected all‐digital DCC with synchronous input clock

This paper presents a fast‐corrected all‐digital duty‐cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty‐cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty‐cycle error of the output clock is between ?2.4 and 2.7%. The largest static phase error between the input and output clock is ?44 ps at 900 MHz. The RMS and peak‐to‐peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18‐µm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm² and dissipates 23 mW with 1.8‐V supply voltage at 900 MHz. Copyright © 2014 John Wiley & Sons, Ltd.     

A low‐power technique for high‐resolution dynamic comparators

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (V_cm) range of 0‐Vdd/2.     

Multiplier‐less VLSI architectures for radix‐22 folded pipelined complex FFT core

The advantages of a multiplier‐less architecture are reduction in hardware and latency. This paper proposes multiplier‐less architectures for the implementation of radix‐2² folded pipelined complex FFT core based on coordinate rotation digital computer (CORDIC) and new distributed arithmetic (NEDA). The number of points considered in the work is sixteen and the folding is done by a factor of four. The proposed designs have been implemented on Xilinx XC5VSX240T‐2FF1738 FPGA and also have been synthesized using the Synopsys design compiler. Proposed designs based on NEDA have reduced area over 83% and based on CORDIC have a reduced area over 78%. The observed slice‐delay product for NEDA based designs are 2.196 and 5.735, and for CORDIC based design is 2.369. Copyright © 2014 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Fast‐squarer circuits using 3‐bit‐scan without overlapping bits

This paper presents a novel technique to design fast‐squaring circuits. The proposed approach speeds up squaring operations combining the 3‐bit scan without overlapping bits and the folding technique. Several hardware implementations of squarer circuits designed as described here are characterized for several operand wordlengths. Obtained results demonstrate that, using the ST 90 nm 1V CMOS technology, a 32‐bit squarer exploiting the novel way of generating partial products reaches a 769 MHz running frequency, dissipates less than 19.3 mW on average and occupies ～91 000µm² of silicon area. Copyright © 2010 John Wiley & Sons, Ltd.     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

GRO‐TDC with gate‐switch‐based delay cell halving resolution limit

In this paper, we propose a time‐to‐digital converter (TDC) with first‐order noise‐shaping. The proposed gated ring oscillator (GRO)‐TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate‐switched configuration to solve the charge redistribution problem. The proposed GRO‐TDC is designed using a 65‐nm process technology, with an area of 0.015 mm² and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO‐TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO‐TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively. Copyright © 2017 John Wiley & Sons, Ltd.