Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Newly proposed hybrid resonant commutation bridge‐leg link snubber‐assisted three‐phase ZVZCS‐PWM soft‐switching inverter

This paper presents the newly proposed hybrid resonant commutation bridge‐leg link (HRCB) snubber circuit which can achieve zero voltage and zero current soft‐switching commutation for single‐phase and three‐phase voltage source‐type inverter, along with its unique features and operation principle. The circuit parameter design approach for the HRCB snubber circuit and the determination estimating scheme of the gate pulse timing processing which is more suitable and acceptable for single‐phase and space voltage vector modulated three‐phase voltage source inverter using the HRCB snubber circuit are described in this paper. In particular, the three‐phase voltage source soft‐switching inverter associated with the proposed HRCB circuits are evaluated and discussed from simulation and experimental viewpoints. The practical effectiveness of the HRCB snubber‐assisted three‐phase voltage source soft‐switching inverter using IGBT power modules which is based on the instantaneous space voltage vector modulation is clarified on the output voltage waveform, actual efficiency of electromagnetic noise in comparison with three‐phase voltage source‐type conventional hard‐switching inverter. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(4): 75–84, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20111     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f² colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = ?109dBc/Hz at f_osc = 12MHz, while consuming 90 μW. A figure of merit of ?161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.     

Extension of the variational equation to analog/digital circuits: numerical and experimental validation

Conventional shooting methods cannot be used to determine the steady‐state solution of circuits whose model is characterised by a vector field exhibiting zero order discontinuities. In the analysis of circuits working on a stable limit cycle, this limitation prevents the use of methods that exploit Floquet theory to compute the variational model and thus the properties of the fundamental matrix and, for example, phase noise in oscillators. In this paper, we use an improved shooting method that solves this drawback by resorting to saltation matrices and show how this method makes possible the correct computation of the first left eigenfunction (known as ppv ) of the fundamental matrix. ppv s are a key aspect in determining phase noise. The results obtained through numerical simulations are compared with measurements on a relaxation oscillator serving as a simple but significant comparison vehicle. Copyright © 2012 John Wiley & Sons, Ltd.     

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal‐oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28‐nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1‐MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd.     

Time‐mode circuits for analog computation

We introduce time‐mode circuits, a set of basic circuit building blocks for analog computation using a temporal step function representation for the inputs and outputs. These novel time‐mode circuits are low power, provide good noise performance and offer improved dynamic range. The design, IC implementation and detailed theoretical signal‐to‐noise ratio (SNR) analysis of a prototype time‐mode circuit—a weighted average computation circuit—are discussed. This new way of computation is studied with respect to existing conventional voltage‐mode and current‐mode circuits. Two possible applications of these time‐mode circuits are presented: an edge detection circuit for 16 pixels and a 3‐tap FIR filter that provides an SNR of 64 dB. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐frequency noise analysis and minimization in Gilbert‐cell‐based mixers for direct‐conversion (zero‐IF) low‐power front‐ends

Low‐frequency (flicker) noise is one of the most important issues in the design of direct‐conversion zero‐IF front‐ends. Within the front‐end building blocks, the direct‐conversion mixer is critical in terms of flicker noise, since it performs the signal down‐conversion to baseband. This paper analyzes the main sources of low‐frequency noise in Gilbert‐cell‐based direct‐conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert‐cell‐based zero‐IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of ?10 dBm, which makes this mixer suitable for a multi‐standard low‐power zero‐IF front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

A 5 GHz quadrature relaxation oscillator with mixing for improved testability or compact front‐end implementation

We demonstrate by measurements on a test circuit that a 5 GHz relaxation oscillator with accurate quadrature outputs and low phase‐noise can be obtained, and that these favorable properties can be preserved while the mixing function is performed by this oscillator. This is useful either to measure the quadrature error at a low frequency, or to implement a low‐intermediate frequency (IF) or zero‐IF (homodyne) radio frequency front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

Discontinuity correction in piecewise‐linear models of oscillators for phase noise characterization

Decomposition of noise perturbation along Floquet eigenvectors has been extensively used in order to achieve a complete analysis of phase noise in oscillator. Piecewise‐linear approximation of nonlinear devices is usually adopted in numerical calculation based on multi‐step integration method for the determination of unperturbed oscillator solution. In this case, exact determination of the monodromy matrix can be hampered by the presence of discontinuities between models introduced by the approximation. In this paper we demonstrate that, without the proper corrections, relevant errors occur in the determination of eigenvalues and eigenvectors, if adjacent linear models presents discontinuities. We obtain this result by the analysis of a simple 2‐D oscillator with piecewise‐linear parameter. We also demonstrate that a correct calculation can be achieved introducing properly calculated state vector boundary conditions by the use of interface matrices. This correction takes into account the effects of discontinuities between the linear models, leading to exact calculation of eigenvalues and eigenvectors, and, consequently, of the phase noise spectrum. Copyright © 2006 John Wiley & Sons, Ltd.     

Subharmonic injection‐locking and self‐oscillating mixing

Subharmonic injection‐locking and self‐oscillating mixing functions of a modified Colpitts oscillator operating at 1 GHz are reported. The injection‐locking circuit, using a GaAs FET, is described theoretically and experimentally. Phase noise, power consumption and conversion gain measurements indicate that the proposed design is attractive for low‐cost, low‐power consumption front‐ends. Copyright © 2008 John Wiley & Sons, Ltd.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Low‐Noise Fully Differential Amplifiers Using JFET‐CMOS Integration Technology for Smart Sensors

In this paper, CMOS‐based low‐noise amplifiers with JFET‐CMOS technology for high‐resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front‐end circuit in many sensor applications. Low‐noise JFET devices are used as input pair of the input differential stages or source‐grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET‐CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET‐CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise‐reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about − 18 dB at 2.5 Hz. JFET‐CMOS technology is very effective in improving the signal‐to‐noise ratio (SNR) of a sensor interface circuit with CMOS‐based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.     

Time‐domain analysis of phase‐noise and jitter in oscillators due to white and colored noise sources

This paper presents an original time‐domain analysis of the phase‐diffusion process, which occurs in oscillators due to the presence of white and colored noise sources. It is shown that the method supplies realistic quantitative predictions of phase‐noise and jitter and provides useful design‐oriented closed‐form expressions of such phenomena. Analytical expressions and numerical simulations are verified through measurements performed on a relaxation oscillator whose behavior is perturbed by externally controlled noise sources. Copyright © 2011 John Wiley & Sons, Ltd.     

New structures of four‐phase oscillators obtained by strongly interweaving mono‐phase limit‐cycle oscillators

The present work is a part of our effort of developing multiphase oscillators. The particular system dealt with here is that of strongly nonlinearly coupled four oscillators that form a multiphase source. Such sources possess potential applications in power electronics, in phased‐array antennas, and in modern methods of modulation and especially in demodulating multi‐phased modulated signals. The present system can be interpreted as embracing four two‐phase oscillators. Nevertheless, as a result of the strong coupling, the second state equation of each oscillator merges with the first equation of the following oscillator. The resulted four‐phase source is, therefore, represented by merely four state equations. The applications related to communications (especially those related to receivers) may be susceptible to the noise performance of the source. We believe that the presently suggested system, which relies on strong coupling of oscillators, is advantageous in its noise performance in comparison to more straightforward recently described multiphase sources, which incorporate loosely coupled oscillators. Copyright © 2007 John Wiley & Sons, Ltd.     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.