Equivalent Circuit of the Bolometer Detector

A small-signal dynamic equivalent circuit is established for the output voltage of a dc-biased bolometer (barretter) detector. The circuit consists of a voltage generator /spl upsi//sub g/, whose output is an undistorted replica of the incident RF-power modulation envelope, followed by a series resistor R/sub 1/ of dynamic origin, a shunt capacitor C that represents heat storage in the bolometer wire, and a series resistor R/sub 0/ equal to the dc resistance, usually 200 ohms. The resistance R/sub 1/ is independent of signal level, and is typically about 220 ohms for an 8.75-mA bolometer and about 120 ohms for a 4.5-mA bolometer. At a modulation frequency f/sub m/ near 0 Hz, the equivalent audio source impedance of the bolometer is R/sub 1/ +R/sub 0/. The common belief that the source impedance is R/sub 0/ in the weak-signal case is, therefore, refuted. Formulas are derived giving v/sub g/ / /P/sub RF/ and R/sub 1/ as functions of basic, easily determined bolometer parameters. The time constant for open-circuit load is /spl tau//sub oc/= R/sub 1/C, where /spl tau//sub oc/ is determined best by measurement, since catalog values of /spl tau//sub oc/ often are seriously in error. The capacitance is C=/spl tau//sub oc/ / /R/sub 1/. With one type of bolometer /spl tau//sub oc/ measures about 110 /spl mu/s, while various catalogs state values of 250 to 350 /spl mu/s. The equivalent circuit is confirmed quantitatively by measurements of output voltage and source impedance versus modulation frequency.     

High-performance inductors integrated on porous silicon

To study the substrate effect on inductor performance, several types of spiral inductors were fabricated on porous silicon (PS), p/sup -/ and p/sup +/ silicon substrate. /spl pi/-network analysis results show that the use of PS effectively reduces the shunt conductance and capacitance. The analysis further shows that the use of PS significantly reduces the eddy current portion of series resistance of inductor, leading to slower increase of the apparent series resistance with increasing frequency. Higher Q-factor and resonant frequency (f/sub r/) result from the reduced shunt conductance, shunt capacitance, and frequency dependence of series resistance. Inductors fabricated on PS regions are subjected to a much less stringent set of constraints than those on bulk Si substrate, allowing for much higher inductance to be achieved without severe sacrifice in Q-factor and f/sub r/. Similarly, much higher Q-factor can be obtained for reasonable inductance and f/sub r/.     

谐振电路品质因数的计算

品质因数是谐振电路中一个非常重要的参数,本文讨论了一般RLC电路谐振时品质因数的计算问题,给出了一般RLC电路谐振时品质因数的简单计算方法,即先计算端口的阻抗或导纳,得到等效的串联或并联电路的R、L、C参数,然后套用串、并联谐振电路的品质因数计算公式即可.作者从品质因数的原始定义入手,说明了根据原始定义计算的品质因数与按照本文给出的方法计算的品质因数计算公式是一致的,从而证明了该方法的正确性.     

Enhanced transmission characteristics of on-chip interconnects withorthogonal gridded shield

On-chip interconnects over an orthogonal grid of grounded shielding lines on the silicon substrate are characterized by full-wave electromagnetic simulation. The analysis is based on a unit cell of the periodic shielded interconnect structure. It is demonstrated that the shielding structure may help to significantly enhance the transmission characteristics of on-chip interconnects particularly in analog and mixed-signal integrated circuits with bulk substrate resistivity on the order of 10 Ω-cm. Simulation results for the extracted R, L, G, C transmission line parameters show a significant decrease in the frequency-dependence of the distributed shunt capacitance as well as decrease in shunt conductance with the shielding structure present, while the series inductance and series resistance parameters are nearly unaffected. An extension of the equivalent circuit model for the shunt admittance of unshielded on-chip interconnects to include the effects of shielding is also presented     

RF Characteristics of a high-performance, 10-fF//spl mu/m/sup 2/ capacitor in a deep trench

We report the properties of a novel polysilicon-insulator-polysilicon trench capacitor with a 380-/spl Aring/ Si/sub 3/N/sub 4/ dielectric that is designed and fabricated for high-frequency bypass and decoupling applications. The capacitor has a specific capacitance as high as 10 fF//spl mu/m/sup 2/ normalized to its footprint area, and a breakdown voltage greater than 15 V at room temperature. The measured S-parameters are in excellent agreement with simulations of an equivalent circuit model that includes a shunt substrate resistance to ground (R/sub sub/). A geometric factor /spl mu/ is defined as the ratio of the imaginary parts of Y/sub 11/ and -Y/sub 21/ at low frequency. The values of /spl mu/ and, consequently, R/sub sub/ are extracted from fitting the measured S-parameter data, and the layout dependence of /spl mu/ and R/sub sub/ is also explained by the model.     

High-Qfactor shunt-switched N-path filters

At its fundamental resonant frequency, a shunt-switched N-path filter is similar to an LCR resonant circuit, except that the selectivity or Q factor achievable, which is a direct function of the passive components employed, may be very much better than normally available in tuned circuits. The limit on the maximum attainable Q factor is shown to depend on the impedance of the shunt arm switches and filter load, as well as the speed of the switches.     

Losses on Multiconductor Transmission Lines in Multilayered Dielectric Media

For the transmission-line modes, a multiconductor transmission line in a multilayered dielectric medium can be characterized by four matrix parameters the capacitance matrices [C], the inductance matrix [L], the shunt conductance matrix [G], and the series resistance matrix [R]. The first two matrices [C] and [L] can be obtained from equivalent electrostatic and magnetostatic problems. The conductance matrix [G] can be obtained by changing all dielectric constants epsilon/sub i/ to complex dielectric constants /angle over epsilon/sub i/ in the equivalent electrostatic problem. The resistance matrix [R] can be obtained by applying a perturbation method to each mode of the transmission line. A computer program has been written for an arbitrary line, and sample computations are presented.     

Physical timing models and design methodology of bipolar nonthreshold logic circuits

Physical timing models have been derived by using the current-domain BJT equivalent circuit for high-speed low-power bipolar NTL circuits. The design methodology of the shunt capacitance C_E and the emitter length of bipolar NTL circuits has also been developed in this study. It is shown that the optimal value of the shunt capacitance C_E is equal to 1–1.25 C_E0 where C_E0 is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both an exact model and a simplified model for C_E0 have been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples.     

Design considerations for high-frequency crystal oscillators

The deleterious effects of crystal shunt capacitance and series resistance on the performance of series-mode oscillators are discussed. When the parasitic capacitance across the crystal significantly modifies the transconductance of the amplifying stage the circuits can become susceptible to a parasitic second mode of oscillation above the series-resonance frequency of the crystal. A simple model that can sufficiently describe such crystal oscillator circuits was developed and used to derive simple design equations that can accurately predict the behavior of these circuits. The design equations should be especially useful for a reliable design in cases when it is not practical to use an additional inductor to compensate for the parasitic shunt capacitance of the crystal. It is shown theoretically that the inclusion of this capacitance in the feedback path reduces the total effective capacitance in the tank circuit, which is tuned to the desired overtone frequency. This creates a second mode of oscillation frequency which is higher than the desired crystal resonance frequency. The ranges of loop-gain and tank resistance values that can prevent this parasitic mode of oscillations are derived. It is also shown that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance     

一种采用LC谐振电路的高频差分有源电感

提出了一种采用LC并联谐振电路的新型差分有源电感,实现了宽的工作频带、高的Q值、较大的电感值和可调谐功能.采用无源电感和MOS晶体管可变电容构成LC谐振电路,减小了等效串联电阻和等效并联电容,在增大电感值、Q值的同时,扩大了工作频带.仿真结果表明,在2～7.6 GHz频率范围内,该新型差分有源电感的电感值大于26 nH...     

Composite right/left-handed transmission line based compact resonant antennas for RF module integration

Several electrically small resonant antennas employing the composite right/left-handed transmission line (CRLH-TL) are presented for integration with portable RF modules. The proposed antenna designs are based on the unique property of anti-parallel phase and group velocity of the CRLH-TL at its fundamental mode. In this mode, the propagation constant increases as the frequency decreases, therefore, a small guided wavelength can be obtained at a lower frequency to provide the small /spl lambda//sub g//2 resonant length used to realize a compact antenna design. Furthermore, the physical size and the operational frequency of the antenna depend on the unit cell size and the equivalent transmission line model parameters of the CRLH-TL, including series inductance, series capacitance, shunt inductance and shunt capacitance. Optimization of these parameters as well as miniaturization techniques of the physical size of unit cell is investigated. A four unit-cell resonant antenna is designed and tested at 1.06 GHz. The length, width and height of the proposed antenna are 1/19/spl lambda//sub 0/, 1/23/spl lambda//sub 0/ and 1/83/spl lambda//sub 0/, respectively. In addition, a compact antenna using a 2-D three by three mushroom like unit cell arrangement is developed at 1.17 GHz, showing that an increased gain of 0.6 dB and higher radiation efficiency can be achieved over the first prototype antenna. The same design is applied in the development of a circularly polarized antenna operating at 2.46 GHz. A 116/spl deg/ beamwidth with axial ratio better than 3 dB is observed. The physical size of the proposed mushroom type small antenna and the circularly polarized antenna is 1/14/spl lambda//sub 0/ by 1/14/spl lambda//sub 0/ by 1/39/spl lambda//sub 0/ and 1/10/spl lambda//sub 0/ by 1/10/spl lambda//sub 0/ by 1/36/spl lambda//sub 0/, respectively.     

Microwave Noise Characterization of GaAs MESFET's: Evaluation by On-Wafer Low-Frequency Output Noise Current Measurement

A simplified noise equivalent circuit is presented for submicron-gate-length MESFET's in the common-source configuration, consisting of five linear circuit elements: the gate-to source capacitance C/sub gs/, the total input resistance R/sub T/, the transconductance g/sub m/, the output resistance R/sub 0/, and a noise current source of spectral density S/sub io/ at the output port. All of these elements can be determined by on-wafer measurements, and the noise current can be measured at a low frequency. The minimum noise figure of the device calculated from this model, as well as the bias and frequency dependence of the noise figure, is shown to be in agreement with microwave noise figure measurements. Thus a technique has been established for determination of the minimum noise figure of a device solely by on-wafer measurements rather than by the usual microwave measurements. The proposed technique can be employed rapidly, conveniently, without the need for tuning, and at the wafer stage of device fabrication.     

Self-heating characterization and extraction method for thermal resistance and capacitance in HV MOSFETs

This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.     

基于Pspice的RTD等效模型及其应用电路研究

简要介绍了RTD(共振隧穿二极管)的微分负阻特性及其等效电路,通过对实际AlAs/InxGa1-xAs/GaAs双势垒共振隧穿结构I-V曲线拟合,得出RTD的Pspice等效电路模型参数。采用Pspice软件建立了RTD的等效电路模型,并对其微分负阻特性进行了仿真,仿真结果与测试结果基本吻合。利用所建立的模型,对RTD的基本应用电路:反相器、非门、与非门和或非门进行了仿真模拟。结果表明,该类电路能够正确实现其逻辑功能。最后,对基于RTD的振荡电路进行了仿真,仿真频率与实际测试频率处于同一数量级。由于实测电路寄生参数如串联电阻、电容等的影响,仿真结果与测试结果稍有出入。     

Determination of source and drain parasitic resistances of HEMTs

A practical method to evaluate the parasitic source resistance R/sub s/ and drain resistance R/sub d/ of high electron mobility transistors (HEMTs) is presented. DC results for R/sub s/ and R/sub d/ can be used as initial values in the determination of linear and nonlinear equivalent circuits by optimisation.<>     

High-isolation CPW MEMS shunt switches. 1. Modeling

This paper, the first of two parts, presents an electromagnetic model for membrane microelectromechanical systems (MEMS) shunt switches for microwave/millimeter-wave applications. The up-state capacitance can be accurately modeled using three-dimensional static solvers, and full-wave solvers are used to predict the current distribution and inductance of the switch. The loss in the up-state position is equivalent to the coplanar waveguide line loss and is 0.01-0.02 dB at 10-30 GHz for a 2-μm-thick Au MEMS shunt switch. It is seen that the capacitance, inductance, and series resistance can be accurately extracted from DC-40 GHz S-parameter measurements. It is also shown that dramatic increase in the down-state isolation (20⁺ dB) can be achieved with the choice of the correct LC series resonant frequency of the switch. In part 2 of this paper, the equivalent capacitor-inductor-resistor model is used in the design of tuned high isolation switches at 10 and 30 GHz     

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.     

Analysis of on-chip spiral inductors using the distributed capacitance model

In this paper, a distributed capacitance model (DCM) for monolithic spiral inductors is developed to predict the equivalent coupling capacitances C/sub p/ between the two terminals and the equivalent capacitance between the metal track and the substrate C/sub sub/. Therefore, the characteristics of inductors such as the S parameter, the quality factor Q, and the self-resonant frequency f/sub SR/ can be predicted by its series inductance, equivalent capacitances, and series resistance. A large number of inductors have been implemented in 0.25- and 0.35-/spl mu/m CMOS processes to demonstrate the prediction accuracy. For planar and multilayer inductors, DCM can provide a quick and accurate assessment to the design of monolithic spiral inductors.     

Measurement of Two-Mode Discontinuities in a Multimode Waveguide by a Resonance Technique

The deliberate use of two or more propagating modes in a multimode waveguide, and a knowledge of associated control elements, has assumed renewed importance, particularly for millimeter wavelength applications. This paper presents a resonance measurement technique for the precise evaluation of the equivalent network for a lossless shunt discontinuity coupling two nondegenerate modes in a multimode waveguide. The discontinuity structure is placed into a cavity closed by adjustable plungers, and the data consists of those plunger positions which render the cavity resonant in the two modes of interest. This multipoint data is then transformed to permit an analysis of the two-port network in the discontinuity plane by conventional techniques. Computations and experimental results obtained at S band illustrative of the procedure are presented for shunt discontinuities coupling the E/sub 01/ and H/sub 01/ modes in circular waveguide. The accuracy achieved is comparable to that obtained in single mode precision measurements.     

A novel approach for miniaturization of slot antennas

With the virtual enforcement of the required boundary condition (BC) at the end of a slot antenna, the area occupied by the resonant antenna can be reduced. To achieve the required virtual BC, the two short circuits at the end of the resonant slot are replaced by some reactive BC, including inductive or capacitive loadings. The application of these loads is shown to reduce the size of the resonant slot antenna for a given resonant frequency without imposing any stringent condition on the impedance matching of the antenna. A procedure for designing this class of slot antennas for any arbitrary size is presented. The procedure is based on an equivalent circuit model for the antenna and its feed structure. The corresponding equivalent circuit parameters are extracted using a full-wave forward model in conjunction with a genetic algorithm optimizer. These parameters are employed to find a proper matching network so that a perfect match to a 50 /spl Omega/ line is obtained. For a prototype slot antenna with approximate dimensions of 0.05/spl lambda//sub 0//spl times/0.05/spl lambda//sub 0/ the impedance match is obtained, with a fairly high gain of -3dBi, for a very small ground plane (/spl ap/0.20/spl lambda//sub 0/). Since there are neither polarization nor mismatch losses, the antenna efficiency is limited only by the dielectric and ohmic losses.