A compatible technique for the formation of thin tantalum film resistors on silicon integrated circuits

A problem in the production of silicon integrated circuits has been yield limitation and applicability restriction due to the large variation and temperature sensitivity of diffused silicon resistors. Use of a thin-film resistive complement on silicon integrated circuits improves performance of many microcircuits heretofore made by the silicon planar process alone. The technique for thin-film on silicon integrated circuits is based on a two-metal resistor-conductor system: tantalum and aluminum. Tantalum was selected as the resistive material because it can be cathodically sputtered with ease, and a wide range of specific resistivity is available as a result of the controlled energy sputtering technique. The process involves production of the active element part of the circuit with standard silicon integrated circuit planar techniques, including contacting the cuts with deposited aluminum. The only deviation from the standard process lies in leaving some unetched SiO2surface area for resistor deposition. Tantalum is cathodically sputtered over the wafer, and delineated by standard photolithographic techniques to form resistor, conductor, and pad areas. A second layer of aluminum is then vacuum deposited over the wafer, and this is delineated to cover the pad and conductor areas of the tantalum with a high conductivity overlay. The exposed tantalum is then thermally stabilized and the final sheet resistivity adjusted by the resulting controlled sheet resistivity increase. The resulting circuits contain stable resistors with tolerance distributions of ±5 percent to ±10 percent, and TCR of -200 to -300 PPM/°C. The silicon active elements in the circuits do not degrade as a result of the thin-film resistor formation.     

Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin

The concept of cut-and-paste customization is introduced for the first time in designing integrated circuits based on mechanically flexible organic field-effect transistors, and is applied to electronic artificial skin. The electronic artificial skin comprise of three separate integrated circuits that are a pressure-sensor array, row decoders, and column selectors to read out pressure information over a large area. All of three integrated circuits are scalable in size because the pressure-sensor array is a simple repetition of sensor cells and the row and column decoders adopt wired-NAND circuits, which enables the cut-and-paste customization in size. The physical cut-and-paste procedure is employed by cutting a part of the integrated circuits and pasting it to another integrated circuit with a connecting plastic tape. The integrated circuits are designed with a standard SPICE simulator and layout design tool, and the operation is confirmed by measurement.     

REGINA test mask: research on EMC guidelines for integrated automotive circuits

This paper presents the results obtained with a specific test mask designed at Motorola for the study of the electromagnetic parasitic emissions in integrated circuits (IC). First, origins of parasitic emissions are presented for CMOS circuits, and electromagnetic compatibility (EMC) measurements of IC emissions are detailed: a radiated measurement method with respect to the IEC61967-2 standard and a conducted one with respect to the IEC61967-4 standard. The REGINA test chip is then described, with a focus on particular structures allowing to test and verify some design guidelines for EMC, like delay cell, emissive structure or on-chip sensor. The printed circuit board that is use to implement the test chip and the experiment test bench are also described. A set of measurements is presented and some guidelines are deduced and recommended as design rules.     

极大规模集成电路测试技术发展

集成电路作为新一代信息战略产业的基础,工艺、封装、应用的发展对测试提出了诸多挑战,同时测试作为集成电路产业链的一环,与设计、制造、封装等环节紧密相联。阐述了集成电路设计中高速、高集成度及测试成本对测试的挑战以及相应的测试解决方案,同时对测试与设计、封装、应用等产业链环节联接的典型技术如测试仿真到测试向量转换、inkless map、测试自动化数据等进行了描述。     

Test Planning for Core-based Integrated Circuits under Power Constraints

This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time.     

The IC yield problem: A tentative analysis for MOS/SOS circuits

Yield on integrated circuits is the result of the contribution of many parameters including number of masking steps, design dimensions, and intrinsic process steps. Test vehicles specific to each process to be investigated are used and through ring oscillators yield figures, and test pattern results, evaluation of yield, as well as identification of main causes of yield loss can be made. The test vehicle approach is consistent with actual LSI circuits yield figures. Defect densities for SOS and bulk processes are compared showing that they are mainly dependent upon the number of critical masking steps and design dimensions.     

集成电路闩锁效应测试

CMOS制程是现今集成电路产品所采用的主流制程。闩锁效应(Latch-up)是指CMOS器件中寄生硅控整流器(SCR)被触发导通后,所引发的正反馈过电流现象。过电流的持续增加将使集成电路产品烧毁。闩锁效应已成为CMOS集成电路在实际应用中主要失效的原因之一。在国际上,EIA/JEDEC协会在1997年也制订出了半静态的闩锁效应测量标准,但只作为草案,并没有正式作为标准公布。我们国家在这方面还没有一个统一的测量标准,大家都是在JEDEC标准的指导下进行测量。文章针对目前国际上通行的闩锁效应测试方法作一个简要的介绍和研究。     

Test quality of hierarchical defect-tolerant integrated circuits

This paper presents a theoretical expression to evaluate the test quality of hierarchical defect-tolerant integrated circuits. This expression, which is developed for circuits with two levels of hierarchy, is based on a defect model with which one can take into account the relative importance (probability of occurrence) of each defect and consequently of each fault. Results obtained from this expression show that, for a given test coverage, the addition of defect-tolerance mechanisms decreases the test quality of integrated circuits. These results are important because they indicate that fault coverage can be a misleading measure of the test quality of defect-tolerant integrated circuits.     

Off-chip Iddq monitor with standard test interface

Off-chip current testing is being considered as an efficient mechanism for improving the quality of electronic systems at the printed circuit board level. This well known fact is linked with the industry accepted testing interface standard IEEE P1149.1 (`Standard test access port and boundary-scan architecture'). A specific integrated circuit with the capability of concurrently measuring the quiescent current level for two integrated circuits under test (ICCUT) is presented with its basis. Architecture and implementation details. All the functions of the monitors are accessible via the standard test access port     

Testing time for ASICs

Application specific integrated circuits (ASICs) have been one of the electronics success stories of the 1980s. The rise in their complexity means that chips are now so complex that it is no longer feasible for a test engineer to understand the design at the level of detail required to generate a test program. ASIC designers are increasingly assuming responsibility for test program development. Fault simulation is discussed and automatic test-vector generation and on-chip test circuits are reviewed     

Variable-shaped e-beam lithography enabling process development for future copper damascene technology

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50 kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200 mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50 nm.     

Electromigration: A review

The aggressive scaling planned for integrated circuits is placing more demands on the materials, processes and designs. The circuits must be reliable and electromigration is a key reliability issue. Because many of the factors that contribute to electromigration are not completely understood, manufacturers must proceed cautiously. In this article electromigration is reviewed from the prospective of the reliability engineer, focusing on those areas of greatest applicability to the manufacturing environment. First, the fundamental physics of electromigration are examined to provide a basis for understanding the factors that affect the lifetimes under the various test conditions. Then, empirical data concerning the impact on reliability of metal stripe geometry, structure and composition are reviewed. The care necessary to make fast, wafer-level tests an important process control tool is discussed. It is shown that pulsed-dc and ac waveforms can provide longer lifetimes than predicted previously, providing some relaxation of current density requirements for higher circuit densities. An understanding of these phenomena is necessary for the reliability engineer to assess today's and tomorrow's integrated circuits.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T _E ) and the Yield Loss (Y _L ) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique.     

Impact of anomalous short-channel MOS transistors on VLSI circuit reliability

In VLSI and ULSI circuits, a major reliability concern is that completed, fully functional, in-specification integrated circuits may contain one or more anomalous transistors with substantially closer source-to-drain spacing than the minimum-design-rule devices, and that such transistors will be more susceptible to degradation or failure due to hot-carrier effects, total-dose-radiation effects or other instabilities. A further concern is that such vulnerable transistors will not be detected during conventional electrical testing or during typical high-reliability integrated circuit burn-in procedures such as static or dynamic burn-in at 125°C, since hot carrier effects tend to anneal out at elevated temperatures, as well as having a negative temperature acceleration factor.Experimental studies have shown that fully functional nMOS transistors with shorter-than-normal channel lengths can have many orders of magnitude greater susceptibility to hot-electron-induced threshold voltage shifts, compared to transistors with minimum-design-rule dimensions of 1.2μm. Total-dose radiation tests showed that anomalous n-channel MOS transistors can have orders-of magnitude higher post-total-dose radiation leakage than nominal devices made by the same process.Several possible types of screening techniques that can be considered for detecting integrated circuits containing anomalous transistors are discussed, including a low-dissipation dynamic stress test at room temperature or at −55°C, with parts electrically characterized before and after the stress test. A large change (delta) of certain critical parameters would be used to predict future failure. Quiescent CMOS supply-current testing could also be used to detect the presence of anomalous transistors in some types of integrated circuits.     

The single-event effect evaluation technology for nano integrated circuits

Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally.     

New test structure for VLSI self-test: the structured test register (STR)

A new test structure which facilitates self-test in digital VLSI integrated circuits is presented. This test structure, termed the structured test register (STR), is constructed by adding some extra components to an otherwise standard BILBO. The advantages of this circuit in terms of increased fault coverage on both the functional and self-test parts of the circuit are described.     

系统芯片的可测性设计与测试

阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。     

镀金盖板上的绿激光标识技术

镀金盖板广泛用于军品集成电路的气密性封装中,其表面标识通常采用油墨移印工艺,但油墨移印的标识在筛选或考核过程中有时存在部分脱落的风险,造成鉴定难以通过。在镀金盖板上的绿激光标识技术,不仅解决了镀金盖板标识脱落的问题,而且解决了高可靠集成电路镀金盖板表面标识产品序列号的工艺难题。激光标识后的样品,顺利通过了按GJB548B要求进行的温度循环、热冲击、耐溶剂和盐雾等可靠性试验。对镀金盖板的激光标识区域进行了电镜扫描和解剖分析的结果表明,标识区域镀金层成份和金层厚度基本没有变化。     

Fault tolerant system based on IDDQ testing

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.