High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

A CMOS Offset Phase Locked Loop for a GSM Transmitter

This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of –163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 s were achieved. The IC was implemented by using 0.35-m CMOS process. It takes 860 m×620 m of total chip area and consumes 17.6 mA with a 3.0 V power supply.     

A Fully Integrated CMOS Phase-Locked Loop with 30 MHz to 2 GHz Locking Range and ±35 ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 m, 2.5 v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 m CMOS technologies. Also it has very low peak-to-peak jitter less than ±35 ps at 1.25 GHz output frequency.     

Surface-Photovoltage Measurement of Volume Electron Lifetime in p-Si Wafers

The problem of estimating the volume lifetime _v of minority carriers in p-type Si wafers by surface-photovoltage measurements is addressed. An experiment is conducted in order to ascertain the relationship between measured and actual values of _v. The measurements are carried out on circular specimens whose thickness is reduced from about 2000 to 450 m by stepwise etching. The specimens are cut from a Czochralski-grown rod, their actual values of _v ranging from 10 to 300 s. The surface recombination rate of minority carriers is determined on both sides of the specimens covered with native oxide, the sides differing in surface finish. The results of the experiment allow one to determine _v up to about 400 s.     

Low-Power Low-Voltage Class-AB Linear OTA for HF Filters with a Large Tuning Range

This letter presents a new low-voltage class-AB differential linear OTA. The proposed transconductor uses a novel scheme based on two cross-coupled class-AB pseudo-differential pairs biased by a Flipped Voltage Follower [1]. The transconductor has been designed using a 0.8 m CMOS technology to operate at 2 V supply voltage with only 260 W of quiescent power consumption. Simulation results show 90 MHz bandwidth with more than two decades of transconductance tuning range.     

1D GaAs Detector Arrays for Digital X-ray Imaging with a 108-μm Spatial Resolution

A 1D x-ray detector array of pitch 108 m is designed, fabricated, and tested. The array is based on the p⁺–n–n–n⁺ structure made in epitaxial GaAs technology. Guard rings are incorporated to reduce detector cross coupling. It is announced that the technology proposed will be used to make arrays with a pitch of 50 m and a spatial resolution of 10 line-pairs/mm, suitable for digital mammography.     

A nonvolatile analog neural memory using floating-gate MOS transistors

Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 m×73 m in a 2-m CMOS process and can retain charge accuracy for over 25 years.This research was partially supported by DARPA under Contracts MDA972-90-C-0037 and MDA972-88-C-0048 and by TRW, Inc.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

Statistical Design of the Four-MOSFET Structure

The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor and values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.     

A Markov modulated fluid queueing system with strict priority

We investigate a Markov modulated fluid queueing system with strict priority. The input process is composed of two fluid flows which are stored in buffer1 and buffer2, respectively. The rates of these fluid flows depend on the current state of a finite state Markov chain. Buffer1 has full assignment of priority (=strict priority) for service and so buffer2 is served at a residual service rate when buffer1 is empty. We explicitly derive the stationary joint distribution of the two buffer contents in the system by a spectral decomposition method. In the case of a twostate Markov chain, the joint distribution is explicitly expressed in terms of the system parameters. Also the joint moments and tail distributions of the two buffer contents are obtained and some numerical examples are presented.     

Personal Imaging and lookpainting as tools for personal documentary and investigative photojournalism

A means and apparatus for covert capture of extremely highresolution photorealistic images is presented. The apparatus embodies a new form of userinterface – instead of the traditional point and click metaphor which was thought to be the simplest photography had to offer, what is proposed is a look metaphor in which images are generated through the natural process of looking around, in a manner that does not require conscious thought or effort. These lookpaintings become photographic/videographic memories that may, at times, exceed the quality attainable with even large and cumbersome professional photographic film cameras, yet they may be captured through a device that resembles ordinary sunglasses. The method is based on longterm psychophysical adaptation using a covert sunglassbased realitymediating apparatus, together with two new results in image processing. The first new result is a means of estimating the true projective coordinate transformation between successive pairs of images, and the second is that of estimating, to within a single unknown scalar constant, the quantity of light arriving at the image plane. Furthermore, what is captured is more than just a picture. The resulting environment map may be explored by one or more remote participants who may also correspond and interact with the wearer during the actual shooting process, giving rise to computer supported collaborative (collective) photography, videography, shared photographic/videographic memory, etc.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

Synthesis of Log-Domain Filters from First-Order Building Blocks

Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 m and 1.2 m BiCMOS processes.     

An Analog Correlator for a WCDMA Receiver

A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma–delta analog-to-digital converter and a second-order sinc type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8–512 depending of the PN code length. The circuit was implemented in 0.8 m CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 m×686 m and the current drain is approximately 370 A.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

Ultra Low Power CORDIC Processor for Wireless Communication Algorithms

We designed and implemented an ultra low power CORDIC processor which targets the implementation of advanced wireless communications algorithms based on Givens rotations and Householder reflections. We propose a modified CORDIC algorithm and architecture, and we elaborate on the low power architectural and algorithmic techniques for minimizing its power consumption. Our CORDIC implementation consumes, in rotate mode, on average 50 W @ 10 MHz under 1 V supply voltage in a .25 m technology.     

0.35 μm CMOS T/R Switch for 2.4 GHz Short Range Wireless Applications

This paper describes the design and implementation of a transmit/receive switch for 2.4 GHz ISM band applications. The T/R switch is implemented in a 0.35 m bulk CMOS process and it occupies 150 m · 170 m of die area. A parasitic MOSFET model including bulk resistance is used to optimize the physical dimensions of the transistors with regard to insertion loss and isolation. The measured insertion loss is 1.3 dB without port matching. Simulations using measured s-parameters indicate that an insertion loss of 0.8 dB can be obtained with a conjugate match. The measured isolation is 42 dB and the maximum transmit power is 16 dBm.     

A 640 by 480 Pixels Readout Circuit for IR Imaging

A readout circuit for a 640 × 480 pixels FPA (focal plane array) has been successfully designed, fabricated and tested. The circuit solution is based on a per pixel source-follower direct injection (SFDI) pre-amplifier. Signal multiplexing is performed in both X and Y direction. The pixel size is 25 m × 25m. The chip is optimized for a QWIP (quantum well infrared photodetector) operating at a temperature of 70 K. The circuit has been realized in a standard 0.8 m CMOS process.