Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

Low power data decision IC for 20-40 Gbit/s data links using 0.2μm AlGaAs/GaAs HEMTs

A decision IC for optical data links at bit rates of 20-40 Gbit/s has been realised by using 0.2 μm AlGaAs/GaAs HEMT technology and tested on-wafer at bit rates up to 25 Gbit/s. The IC can be operated with a supply from ~3.3 to 5.2 V and a DC current of ~50 mA     

An 8-bit-resolution, 360-μs write time nonvolatile analog memorybased on differentially balanced constant-tunneling-current scheme(DBCS)

This paper describes a fast and accurate nonvolatile analog memory (NVAM) and its programming scheme. Both constant programming rate and single-pulse programmability have been achieved, which drastically enhance programming speed and accuracy. A prototype chip containing 8×128 NVAM cells (cell size of 9×13.6 μm²) has been fabricated using 0.8-μm CMOS. Each cell is measured to store more than eight bit levels within 360 μs     

An in-system reprogrammable 32 K×8 CMOS flash memory

The authors describe the design and performance of a 192-mil² 256 K (32 K×8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.5 μm EPROM base technology with a one-transistor 6×6-μm² cell, the device electrically erases all cells in the array matrix in 200 ms and electrically programs at the rate of 100 μs/byte typical. The read performance is equivalent to comparable-density CMOS EPROM devices with a chip-enable access time of 110 ns at 30-mA active current consumption. A command-port interface facilitates microprocessor-controlled reprogramming capability. Device reliability has been increased over byte-alterable EEPROMs by reducing the program power supply to 12 V. Cycling endurance experiments have demonstrated that the device is capable of more than 10000 erase/program cycles     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm² has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm², and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm² by using the minimal cell size (2.0×10 μm²)     

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm². The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm² because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta₂O₅ film equivalent to a 2.8-nm SiO₂ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

A high gain n-well/gate tied PMOSFET image sensor fabricated from astandard CMOS process

The performance of a high gain photodetector fabricated using a standard 0.8-μm, triple metal, n-well CMOS process is reported, The photodetector is formed by connecting the gate of the PMOSFET and n-well together while keeping both floating. The depletion region induced by the floating gate and the well-to-substrate p-n junction separate the optically generated electron-hole pairs in the direction perpendicular to the current flow. The n-well potential modulated by illumination is fed back to the gate through the well-to-gate connection, which results in an extra current amplification beyond that of a normal PMOSFET biased in the lateral bipolar mode. A high responsivity of 2.5×10³ A/W has been measured with an operating voltage as low as 0.3 V for a W/L of 8.2 μm/0.8 μm. The impact of technology scaling on the performance of the photodetector are also studied. A simple 32×32-pixel image sensor array was fabricated to demonstrate the feasibility of integrating the new device in actual circuit applications     

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 μm² and a die size of 42.9 mm² have been achieved with 0.8 μm design rules. Read access time and search access time are 115 ns and 135 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access     

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 μm to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si₃N₄ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6×10⁶ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns     

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm², using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm², which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved     

A high sensitivity lead-titanate (PbTiO3) pyroelectricthin-film infrared sensor with temperature isolation improvementstructure

An infrared (IR) sensor with the lead-titanate (PbTiO₃) thin-film using the technology of micro-electromechanical system to achieve a better thermal isolation structure has been fabricated and developed, The major IR-sensing part on the cantilever beam with dimensions of 200×100×2 μm³ consists of a 500 Å PbTiO₃ layer deposited by RF sputtering, and an evaporated bismuth (Bi) layer. This thermal isolation improved structure exhibits a much superior performance to that of a traditional IR-sensing bulk structure on the experimental results, which show a 200% and 300% improvement in current gain under the incident optical power 500 μW and 6 V applied bias at room temperature and 77 K, respectively,     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

A 2-D velocity- and direction-selective sensor with BJT-basedsilicon retina and temporal zero-crossing detector

In this paper, a 2-D velocity- and direction-selective visual motion sensor with a bipolar junction transistor (BJT)-based silicon retina and temporal zero-crossing detector is proposed and implemented. In the proposed sensor, a token-based delay-and-correlate computational algorithm is adopted to detect the selected speed and direction of moving object images. Moreover, binary pulsed signals are used as correlative signals to increase the velocity and direction selectivities. Each basic detection cell in the sensor has a compact architecture, which consists of one BJT-based silicon retina cell, one current-input edge extractor, two delay paths, and four correlators. Using the proposed architecture, an experimental 32×32 visual motion sensor chip with a cell size of 100×100 μm² has been designed and fabricated by using 0.6-μm CMOS technology. The correct operations of the fabricated sensor chip have been verified through measurements. The measured ranges of selectively detected velocity and direction in the fabricated sensor chip are 56 mm/s-5 m/s and 0-360°, respectively. The complete sensor system consumes 20 mW at 5 V     

A 6.75 ns 16×16 bit multiplier in single-level-metal CMOStechnology

A 16×16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 μm devices     

An asynchronous GaAs MESFET static RAM using a new current mirrormemory cell

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm² and cell current of 60 μA were achieved using a conventional E/D process     

A novel memory cell for multiport RAM on 0.5 μm CMOSSea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V