CMOS VHF transconductance-C lowpass filter

Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response.<>     

Current-mode differential wave active filters

A technique for obtaining differential active filters suitable for integrated circuit implementation is presented. These filters, based on current-mode differential-wave active blocks, can operate at high frequencies. The cutoff frequency can by tuned by the bias current. The proposed filter topologies are modular and very flexible for both the electronic and the physical design. Simulation results of a third-order elliptic filter, designed in a 0.35-/spl mu/m CMOS technology, are presented.     

Linear CMOS transconductance element for VHF filters

A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, V/sub ipp/=1.8 V), nondominant poles in the gigahertz range and a 40 dB DC gain.<>     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

具有寄生极点的二阶电流模式滤波器的可调性

积分器寄生极点离主极点不是很远时,会引起全集成滤波器参数的偏差。文中分析了积分器有限直流增益和非主极点的影响,给出了二阶滤波器极点频率和品质因数的微变公式,研究了滤波器的可调控性。在此基础上,提出了增益可调型电流模式连续时间积分器,用这种积分器实现的滤波器能实现fp和Q的双调控。     

Electronically Tunable Microwave Bandstop Filters

The design procedures for varactor tuned bandstop filters are presented. A novel circuit technique for realizing bandstop filters with a symmetrical frequency response is described and explicit design formulas are presented. The physical design and experimental performance of a three cavity varactor tuned bandstop filter tunable around 4 GHz is presented. Experimental results are substantiated with computer analysis which includes the effects of varactor resistance.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

适宜集成的KHN滤波器设计

为了获得高精度的电压模KHN滤波器,以Deboo积分器为原型,先给出一种高精度、易集成的变形Deboo积分器,再借助Meson公式,用变形Deboo积分器设计出极点频率为31.8 kHz、品质因素为1、通带增益为2的通用电压模KHN滤波器.该电路不仅可同时实现高通、带通和低通输出,且极点频率与品质因素能实现正交、精确调节,电路的参数取决于电阻比,两积分电容接地,因而适合单片集成技术.计算机仿真结果与理论分析一致.     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

A 230-nW 10-s time constant CMOS integrator for an adaptive nerve signal amplifier

This paper describes a micropower CMOS integrator with an extremely large time constant for use in a variety of low-frequency signal processing applications. The specific use of the integrator in an implantable biomedical integrated circuit is described. The integrator is based on the OTA-C approach and a very small transconductance of 100 pA/V was achieved by cascading a short chain of transconductance-transimpedance stages. The time constant of the integrator is tunable between about 0.2 and 10 s, and any offset voltages at the output terminal can be trimmed out. The circuit was fabricated in a 0.8-/spl mu/m CMOS process, dissipates 230 nW from /spl plusmn/1.5 V power supplies (excluding the bias circuitry and output buffers) and has a core area of 0.1 mm/sup 2/. The integrator offers superior performance in terms of power consumption, die area and time constant when compared to previously published work.     

Digitally tuned analogue integrated filters using R-2R ladder

A new technique for designing digitally tuned frequency selective analogue integrated circuits is proposed. The technique incorporates the R-2R ladder as a circuit element into the circuit design to provide precise frequency characteristics that can be tuned over a wide range. Two filters are described to illustrate the proposed approach. The proposed filters are used to implement the lowpass channel-select filter of a multi-standard direct conversion wireless receiver and the bandpass filter of a low IF frequency-hopping receiver     

MOSFET capacitor filters using unity gain CMOS current conveyors

A CMOS current conveyor and a MOSFET-capacitor integrator are presented. High frequency integrated filters can be constructed based on this integrator. Simulation results demonstrate that a third order lowpass ladder filter can achieve a wide bandwidth up to 1.0 MHz.<>     

Differential current-mode tunable wave active filters based on single-ended wave port terminators

A method for the design of differential current-mode wave active filters, which is based on the use of single-ended wave port terminators, is presented in this paper. The resulting filters are modular and very simple to design while their cutoff frequency is controlled by a dc current, giving them the ability of frequency tuning. As an example a wide-band bandpass filter is realized by cascading a low-pass and a highpass filter. The overall filter has been integrated using a standard 0.35-/spl mu/m CMOS technology.     

Continuous-Time 4th Order Butterworth Low-Pass Filter for Video Frequency Applications

In this paper, a continuous-time 4th order Butterworth low-pass filter based on current-mode processing is presented for applications over the video frequency range. A new type of integrator in which both voltage and currents may be integrated is presented and used as the main active block. The filter has been implemented using a very low-cost 2.4 m CMOS process (Mietec). The whole circuit occupies 2.8 mm² and consumes 19 mW from a ±1.5 V supply. Experimental results are given for a 4.5 MHz to 12 MHz tunable low-pass filter with 58 dB of dynamic range at 10 MHz.     

A CMOS continuous-time Gm-C filter for PRML read channelapplications at 150 Mb/s and beyond

Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (G_m) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (f_c) range of 6-43 MHz, where f_c is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within ±2% for frequencies below 1.75 f _c. The cutoff frequency exhibits a 650 ppm/°C temperature dependency and a variation of ±1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (V_nominal=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-μm single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm²      

Current-mode continuous-time filters using complementary current mirror pairs

A design of current-mode continuous-time filters for low voltage and high frequency applications using complementary bipolar current mirror pairs is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integration. Since the filters are based on the integrator type of realization, the proposed method can be used for a wide range of applications. The frequency of the filters can easily be changed by the DC controlling current. A fifth-order Butterworth and a third-order leapfrog filter with tunable cutoff frequencies from 20 MHz to 100 MHz are designed as examples and simulated by SPICE using standard bipolar parameters.     

基于OTRA电流模式二阶通用滤波器的设计

鉴于单个OTRA电流模式滤波器未见报道,以CCⅡ二阶通用电流模式滤波器为原型,利用1个OTRA,1个MOS电压跟随器,1个CMOS电压反相器,3个电阻和2个电容,构成了二阶通用电流模式滤波器,可同时获得高通、带通和低通输出。与传统电路相比,该电路能减小寄生电容的影响,因而有较高的稳定性;调节极点角频率与品质因素的元素多,因而调整方便,且通带增益可调范围广,无源灵敏度较低,电路结构简单,便于电控调谐,特别适合单片集成技术。     

一种对数域电流模式积分器及其在高频滤波中的应用

提出了一种新颖的对数城电流模式积分器。该积分器的时间常数由参考偏置电流控制。用该积分器设计了二阶带通滤波器和0．1dB纹波三阶Chebyshev低通滤波器。计算机仿真表明，所设计的滤波器实际频响特性几乎是理想的，而且高频谐波失真很小，通频带灵敏度很低，频率在很宽的范围内可控。电路由双极型晶体管和接地电容构成，适合于全集成实现。     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

Log-domain all pass filter based on integrators

A new all-pass (AP) Log-domain filter is presented. The circuit is based on integrator loop and the current sources. The filter circuit has a very simple structure since it uses only bipolar junction transistors (BJT’s) and a grounded capacitor. The configuration offers large dynamic range at low power supply and higher frequency operation. The filter has a large bandwidth due to its inherent current-mode (CM) nature and Log-domain properties. Phase angle can be electronically tuned through the bias current. The circuit can be implemented in integrated form. PSPICE simulations are given to confirm the theoretical analysis.