基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

复合量子点MOSFET结构存储器的电路模拟

本文采用准经典近似的Monte Carlo方法对复合量子点MOSFET结构存储器的等效单电子电路进行了模拟.研究结果表明,由于台阶状的复合隧穿势垒的作用,存储器的存储时间特性可得到极大提高.我们进一步研究了N沟道锗/硅复合量子点MOSFET结构存储器的时间特性,得到其存储时间可长达数年,同时写擦时间可分别为μs和ns量级,从而这种新型的器件结构可以有效解决快速编程和长久存储间的矛盾.     

p沟道锗/硅异质纳米结构MOSFET存储器及其逻辑阵列

采用巴丁(Bardeen)传输哈密顿方法,数值计算了p沟道锗/硅异质纳米结构存储器的时间特性.由于台阶状隧穿势垒和较高价带带边的作用,这种新型的存储器单元可以同时实现器件的快速编程和长久存储,具有优异的存储特性.以2×2逻辑阵列为例说明了这类存储器单元组成逻辑电路的设计原理.研究结果表明:这种器件可以作为在室温下工作的性能优异的非易失性存储器单元,有望在将来的超大规模集成电路中获得应用.     

p沟道锗/硅异质纳米结构MOSFET存储器及其逻辑阵列

采用巴丁(Bardeen)传输哈密顿方法,数值计算了p沟道锗/硅异质纳米结构存储器的时间特性.由于台阶状隧穿势垒和较高价带带边的作用,这种新型的存储器单元可以同时实现器件的快速编程和长久存储,具有优异的存储特性.以2×2逻辑阵列为例说明了这类存储器单元组成逻辑电路的设计原理.研究结果表明:这种器件可以作为在室温下工作的性能优异的非易失性存储器单元,有望在将来的超大规模集成电路中获得应用.     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

硅纳米晶存储器的耐受性研究

首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。     

可嵌入式应用的新型2T结构硅纳米晶存储器

本文研究了2T硅纳米晶非挥发存储器性能和可靠性。存储单元可获得良好性能,包括低压操作下快速的擦写速度,卓越的数据保持特性（保持10年）,良好的耐受性（10k次擦写周期以后小于10%的阈值电压飘移）。数据表明了此器件在未来嵌入式非挥发存储应用的可能性。     

Si基纳米结构的电子性质

各种Si基纳米发光材料在Si基光电子器件及其全Si光电子集成技术中具有潜在的应用前景,从理论和实验上对其电子结构进行研究,有助于我们深化对其发光机制的认识与理解。本文主要从量子限制效应发光这一角度,着重介绍了Si纳米晶粒、Ge/Si量子点,SiO2/Si超晶格和超小尺寸Si纳米团簇等不同Si基纳米结构的电子性质以及它们与发光特性之间的关系。还讨论了介质镶嵌和表面钝化对其电子结构的影响。     

JVD silicon nitride as tunnel dielectric in p-channel flash memory

High-quality jet vapor deposition nitride is investigated as a tunnel dielectric for flash memory device application. Compared to control devices with SiO₂ tunnel dielectric, faster programming speed as well as better retention time are achieved with low programming voltage. The p-channel devices can be programmed by hot electrons and erased by hot holes, or vice versa. Multilevel programming capability is shown     

Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory

The investigations on the nanowire width (W) dependence of memory performance including P/E (programming and erasing) speed, data retention time and endurance characteristics in nanowire SONOS flash memory have been performed through the measurement and the device simulation. From measured results, a narrow device has advantages in terms of a fast P/E speed and the endurance characteristics. However, a narrow device has disadvantage in terms of the decreased data retention time. Another disadvantage of a narrow device is expected to the large power consumption due to large GIDL (Gate Induced Drain Leakage) current. The device simulation was performed to explore the causes for a fast P/E speed, an enhanced endurance characteristics and the reduced data retention time in narrow devices.     

An asymmetric two-side program with one-side read (ATPOR) device for MultiBit per cell MLC nitride-trapping flash memories

An asymmetric two-side program with one-side read (ATPOR) Flash memory device is proposed. In this nitride-trapping device, the interaction of stored charges in the two sides (second-bit effect) is utilized to achieve multilevel cell (MLC) V/sub t/ levels with the advantages of relatively small total charge. The small total charge can enhance both programming and erasing efficiency. The ATPOR device with programming and erasing times within 100 ns and 40 /spl mu/s are demonstrated. Excellent read disturb immunity of ATPOR device can provide high scaling capability. In addition, good data retention and P/E cycling endurance and reliability are achieved. For 2-bit/cell and 3-bit/cell MLC applications, the ATPOR device with tight level distributions less than 100 mV is illustrated.     

Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

The nonvolatile memory properties of the partially crystallized HfO₂ charge storage layer are investigated using short-channel devices of gate length L_g down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of L_g > 170 nm, although the reduction of the memory window is observed for devices of L_g < 170 nm. A memory window of 5.5 V, ten-year retention of V_th clearance larger than 1.5 V between adjacent levels, endurance for 10⁵ programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO₂ shows a larger memory window than HfO₂ nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO₂ matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, V_th control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si₃N₄ trapping layer.     

P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

A flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V_th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled flash memory cells. Both device simulation and experimental verification are presented.     

Nonvolatile flash memory device using Ge nanocrystals embedded in HfAlO high-/spl kappa/tunneling and control oxides: Device fabrication and electrical performance

We fabricated a nonvolatile Flash memory device using Ge nanocrystals (NCs) floating-gate (FG)-embedded in HfAlO high-/spl kappa/ tunneling/control oxides. Process compatibility and memory operation of the device were investigated. Results show that Ge-NC have good thermal stability in the HfAlO matrix as indicated by the negative Gibbs free energy changes for both reactions of GeO/sub 2/+Hf/spl rarr/HfO/sub 2/+Ge and 3GeO/sub 2/+4Al/spl rarr/2Al/sub 2/O/sub 3/+3Ge. This stability implies that the fabricated structure can be compatible with the standard CMOS process with the ability to sustain source-drain activation anneal temperatures. Compared with Si-NC embedded in HfO/sub 2/, Ge-NC embedded in HfAlO can provide more electron traps, thereby enlarging the memory window. It is also shown that this structure can achieve a low programming voltage of 6-7 V for fast programming, a long charge retention time of ten years maintaining a 0.7-V memory window, and good endurance characteristics of up to 10/sup 6/ rewrite cycles. This paper shows that the Ge-NC embedded in HfAlO is a promising candidate for further scaling of FG Flash memory devices.     

P-channel Ge/Si Hetero-nanocrystal Based MOSFET Memory

The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide T_ox=2nm and the dimensions of Si- and Ge-nanocrystal D_Si=D_Ge=5nm, the retention time of this device can reach ten years(~1×10~8s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage |V_g|=3V with respect to N-wells, respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature, is desired to obtain application in future VLSI.     

Improved retention characteristic of charge-trapped flash device with sealing layer/Al2O3 or Al2O3/high-k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al₂O₃ as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al₂O₃/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al₂O₃ as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al₂O₃/high-k stacked blocking layer approaches, retention property can be further improved.     

Numerical investigation of characteristics of p-channel Ge/Si hetero-nanocrystal memory

The characteristics of p-channel Ge/Si hetero-nanocrystal based MOSFET memory have been investigated numerically considering mainly hole-tunneling process. Owing to the advantages of a compound potential well and a higher band offset at the valence band compared with the p-channel Si nanocrystal based MOSFET memory and n-channel Ge/Si hetero-nanocrystal based MOSFET memory, the present structure shows that the holes have a longer retention time. Moreover, this kind of device keeps on having high-speed writing/erasing in the direct-tunneling ultrathin oxide regime. It would be expected to solve the contradictory problem between high-speed programming and long retention, therefore, the performance would be substantially improved.     

Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory

High-quality silicon-nitride (Si/sub 3/N/sub 4/) formed by rapid thermal nitridation is investigated as the tunnel dielectric in a SONOS-type memory device for the first time. Compared to a conventional thermal SiO/sub 2/ tunnel dielectric, thermal Si/sub 3/N/sub 4/ provides 100/spl times/ better retention after 1e5 P/E cycles and better endurance characteristics with low programming voltages. Hence, the SONNS structure is promising for nonvolatile memory applications.