Circuit modeling of collector current spreading effects in quasi-saturation for advanced bipolar transistors

The advanced bipolar transistor operating in the quasi-saturation region has been modeled, including collector current spreading effects. It is shown that the multidimensional collector current spreading, resulting from high carrier concentration gradient in the collector, ameliorates quasi-saturation effects in the d.c. and transient operation. The mechanism of collector spreading is investigated by physical device simulations. SPICE circuit simulations employing the collector spreading model are compared with measurements and are found to be in excellent agreement.     

Gigabit logic bipolar technology: advanced super self-aligned process technology

A practical bipolar logic circuit, a three-stage frequency divider, has been made with advanced super self-aligned process technology (a halfmicron bipolar technology), which has been operated at clock frequencies up to 5.5 GHz.     

Merged CMOS/bipolar current switch logic (MCSL)

A merged CMOS/bipolar current switch logic (MCSL) is presented. CMOS/ECL level conversion and logical operation are realized simultaneously. This circuit technique allows a supply voltage reduction to 3.3 V. A carry delay time of 150 ps/bit for a 4-bit BiCMOS full adder was measured. This is about five times faster than an optimized CMOS adder.<>     

A low-distortion bipolar feedback current amplifier technique

A bipolar current amplifier using modified Wilson current mirrors in a feedback configuration to avoid the effects of voltage modulation is presented. An output of 20-mA ppk has been obtained with only 1-percent harmonic distortion irrespective of load and with proportionally lower distortion at reduced output current.     

一种基于标准逻辑单元的GALS异步封装电路

基于点对点GALS模型,给出了异步封装电路的信号状态转换图(STG),基于Petrify设计了一种基于标准逻辑单元的GALS异步封装电路,包括同步/异步接口电路、具有分频及暂停功能的局部时钟等设计.由于所设计的异步封装电路具有不存在延时器件、没有使用特殊的异步逻辑单元等特点,所以论文基于两个同步计数器实现了GALS点对点模型进行仿真和FPGA验证,结果显示了整个异步封装及其GALS系统性能的正确性.     

超深亚微米可制造标准单元库设计

当集成电路的特征尺寸下降到100nm以下,可制造性设计就变得尤为重要。本文提出了一种65nm可制造性标准单元库的设计方法。通过精简基本单元的数量,降低光学矫正的时间和空间复杂度;利用DFM设计规则和光学模拟仿真对每个单元的版图进行优化以提高整个单元库的可制造性。应用该方法实现的标准单元库在时序,功耗,面积方面与传统标准单元库相比具有很好的性能,并且通过Foundry的TD部门65nm工艺线的可制造性测试,有利于65nm工艺生产良率的提升。     

Computer-aided device modeling and design procedure for current hogging logic (CHL)

Modeling of functional devices requires computer simulation of lateral and vertical device structure due to geometrical complexity. It not only must meet the requirements of network analysis programs, but also has to enable quantitative design. For the basic element of current hogging logic (CHL), the computer simulation of the two-dimensional situation has resulted in and given justification for a simple model approximating the injection performance and enabling quantitative design of even complex CHL circuits.     

High-performance logic and high-gain analog CMOS transistors formedby a shadow-mask technique with a single implant step

Transistors have been fabricated with a photoresist mask placed in close proximity to the gate so as to effectively block the angled halo implant from the gate region. Devices for which the halo has been eliminated demonstrate superior drain conductance, while devices with the halo implant show the short-channel effect required for high performance. Asymmetric devices have also been fabricated in a similar manner, producing devices with improved analog characteristics without an additional masking layer     

A bipolar device modeling technique applicable to computer-aided circuit analysis and design

The development of a modeling technique for bipolar devices is described. The application of the technique results in complete and realistic large-signal models which are amenable to computer-aided analysis. SCEPTRE has been used to effectively analyze derived models, and results of SCEPTRE analyses of a developed transistor model are presented to illustrate the general capabilities of the modeling technique and to indicate the efficiency with which the resulting models are handled by SCEPTRE. The models are structured such that systematic modifications in model complexity can be effected to reflect refinements in the states of the art of device processing and analysis, as well as to efficiently satisfy the user's model capability requirements.     

MODEL AND MODELING OF LOW TEMPERATURE CURRENT GAIN OF POLYSILICON EMITTER BIPOLAR TRANSISTORS

A unified model of low temperature current gain of polysilicon emitter bipolar transistors based on effective recombination method is presented, incorporating band-gap narrowing, carrier freezing-out, tunneling of holes through polysilicon/silicon interface oxide layer and reduced mobility mechanism in polysilicon. The modeling results based on this model are in good agreement with experimental data.     

A knowledge-based test generator for standard cell and iterative array logic circuits

The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high-level test knowledge in conjunction with low-level structural information to generate tests for the circuit.<>     

Modeling the reverse base current phenomenon due to avalancheeffect in advanced bipolar transistors

A model of reverse base current characteristics which is based on device physics is presented. The model requires only physical parameters, thus allowing circuit designers to estimate the device performance under avalanche operation prior to the actual device fabrication. Previously reported experimental data are included in support of the model     

新型数字逻辑标准及接口技术

由于应用需求的驱动,近几年产生了许多新型数字逻辑标准,本文从其物理连接特性着手进行归纳,最后讨论了它们的应用及相互间的接口技术。     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

An effective timing characterization method for an accuracy-proved VLSI standard cell library

This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.     

Design and evaluation of a bipolar tri-state logic family

A three-valued bipolar logic family utilizing the two conventional TTL logic states plus the high impedance state is described. The functions realized permit the use of existing synthesis algorithms. The noise immunity for such circuits is defined and calculated. A comparison of circuit complexity between the three-valued family and binary TTL is made for three- and two-valued functions with approximately the same number of possible inputs.     

Compact modeling of the noise of a bipolar transistor under DC and AC current crowding conditions

The effect of current crowding on dc, on ac, and in particular on the noise characteristic of bipolar transistors, is studied. An equivalent circuit able to model these effects is presented. General formulations to calculate current crowding in arbitrary geometries are derived. Both rectangular and circular geometries are discussed in detail.     

Reverse modeling of E/D logic submicrometer MODFETs and predictionof maximum extrinsic MODFET current gain cutoff frequency

A method for estimating the source resistance, fringe capacitance, gate length, and effective saturation velocity from the microwave Y -parameters of MODFETs with known vertical structure is discussed. The scheme is applied to a variety of MODFETs fabricated on molecular-beam-epitaxial (MBE) material using a submicrometer enhancement/depletion- (E/D-) mode IC process. More than 100 MODFETs were measured and analyzed. Both the values and variances of the extracted parameters are very physical. In particular, it is found that the extracted saturation velocity (1) is independent of the gate length in the regime studied (0.25-0.91 μm); (2) is rather independent of process and threshold voltage variations; (3) is marginally higher when the Al mole fraction is increased from 20% to 28%; (4) is not significantly higher in pseudomorphic InGaAs than in GaAs; and (5) is quite a bit higher than is often assumed or extracted, with a value close to the stationary peak velocity in undoped GaAs. There is little sign of overshoot above this limit. Using the extracted peak velocity and a simple analytical MODFET model, the extrinsic current gain cutoff frequency (f_Tx) is predicted well in the gate-length regime studied     

High-speed, low-power, bipolar standard cell design methodology forGbit/s signal processing

A low-power Si bipolar standard cell LSI design methodology for gigabit/second signal processing is described. To obtain high-speed operation, it features a pair of differential clock channels inside cells, differential clock distribution with the placement of differential wires of equal length and load, a performance-driven layout, and a highly accurate static timing analysis. A computer-aided-design-based optimization technology for power dissipation makes cell currents minimum while maintaining the circuit speed. A 5.6-K gate synchronous digital hierarchy signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design method     

An automatic parameter extraction technique for advanced CMOS device modeling using genetic algorithm

We in this paper present an computational intelligence technique to extract semiconductor device model parameters. This solution methodology is based on a genetic algorithm (GA) with an exponential type weight function, renew operator, and adaptive sampling scheme. The proposed approach automatically extracts a set of complete parameters with respect to a specified compact model, such as a BSIM model for deep-submicron and nanoscale complementary metal-oxide-semiconductor (CMOS) devices. Compared with conventional artificial step-by-step fitting approaches, the proposed extraction methodology automatically tracks the shape variation of current-voltage (I-V) curves and examines the first derivative of I-V curves; therefore, highly accurate results can be obtained directly. Applying the renew operator will keep the evolutionary trend improving by removing the individuals without mainly features. The sampling strategy will speed up the evolution process and still maintain the extraction accuracy in a reasonable range. A developed prototype is successfully applied to extract model parameter of N- and P-metal-oxide-semiconductor field effect transistors (MOSFETs). This optimization method shows good physical accuracy and computational performance, and provides an alternative for optimal device modeling and circuit design in nanodevice era. Genetic algorithm based automatic model parameter extraction bridges the communities between circuit design and chip fabrication; in particular, it will significantly benefits design of system-on-a-chip.