Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

On the design parameters of flip-chip PBGA package assembly foroptimum solder ball reliability

An experimental investigation of the warpage of a flip-chip plastic ball grid array package assembly is presented and a critical deformation mode is identified. The experimental data, documented while cooling the assembly from the underfill curing temperature to -40°C, clearly reveal the effect of the constraints from the chip and the PCB on the global behavior of the substrate. The constraints produce an inflection point of the substrate at the edge of the chip. An experimentally verified three-dimensional (3-D) nonlinear finite element analysis proceeds to quantify the effect of the substrate behavior on the second-level solder ball strains. An extensive parametric study is conducted to identify the most critical design parameter for optimum solder ball reliability     

Wafer-applied underfill: flip-chip assembly and reliability

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.     

New IC package, assembly technique by means of a "blind" alignment "flip-chip" method and assembling facilities

In spite of a long period of the development ofmicroelectronic components base, the problem of the creation of IC package design, providing minimal area losses in contrast with area of a chip, remains unsolved [1]Area losses can be described by the parameter P,which is equal to the ratio between the package area in plan and the chip area:     

Evolution of a unique flip-chip MCM-L package

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to become the packaging method of choice, particularly for >200 I/O applications. FC packages come in a variety of styles: FC plastic ball grid arrays (FC/PBGAs), FC plastic quad flat packs (PC/PQFPs), etc. Presently, the industry's drive is toward single chip packages on low cost laminates; i.e., organic substrates. Work is starting to occur in the area of multichip FC packages, due to the need to increase memory to microprocessor speed communication. In this article, a unique FC/MCM-L package is discussed. Part I will concentrate on the development and reliability testing of a one to four chip leadless FC/MCM-L package. Unlike traditional surface mount (SM) components that are attached to printed wiring boards (PWBs) with leads, the SM pads within the body of the package are used for attachment to a PWB. Collapsible eutectic solder domes are deposited on the SM pads by traditional screen printing. After reflow, these domes are used to connect the FC/MCM-L to the PWB. Challenges encountered during package design, PWB fabrication and first and second level assembly will be discussed. Part II of this article will focus on the extension of this FC/MCM-L package to a BGA second level interconnect. Change of FC attachment method, design enhancements, assembly, and reliability testing results will be presented     

Underfill constraint effects during thermomechanical cycling of flip-chip solder joints

The presence of an “underfill” encapsulant between a microelectronic device and the underlying substrate is known to substantially improve the thermal fatigue life of flip-chip (FC) solder joints, primarily due to load-transfer from the solder to the encapsulant. In this study, a new single joint-shear (SJS) test, which allows the measurement of the strain response of an individual solder ball during thermomechanical cycling (TMC), has been used to investigate the impact of the constraint imposed by the underfill on a solder joint. Finite element (FE) modeling has been used to demonstrate that the SJS sample geometry captures most of the deformation characteristics of an FC joint and to provide insight into experimental observations. It has been shown that the strain response of a eutectic Pb-Sn solder joint is influenced significantly by in-situ microstructural coarsening during TMC, which in turn is dependent on the underfill properties. In general, underfill properties, which allow the imposition of large compressive-hydrostatic stresses on the solder joint, were the most effective in reducing coarsening. Phase coarsening prevented the stabilization of the stress-strain response of the solder, even in the absence of crack damage, and was found to depend strongly on the local inelastic-strain state within the joint. This necessitates that future solder deformation models account for strain-history-dependent microstructural evolution and that underfill properties be optimized to minimize the extent of coarsening during TMC in order to maximize joint life.     

Electrical evaluation of flip-chip package alternatives for nextgeneration microprocessors

Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-grid-array (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages     

Study of package warp behavior for high-performance flip-chip BGA

To meet the future needs of high pin count and high performance, the LSI die and package size of flip-chip BGA (FC-BGA) devices have become larger. As a result, package warpage due to mismatch of the coefficients of thermal expansion among the construction materials has become a more serious problem for package reliability. In this paper, package warpage is successfully measured by a 3-D surface profile method in the temperature range from −55 to 230 °C. Furthermore, the package warpage of FC-BGA was investigated to clarify the effect of the thermomechanical properties of the underfill resin. Based on the results, we constructed a model of the mechanism of package warpage. This paper proposes an optimized underfill resin that can achieve low package warpage and a long fatigue life of the solder bump. The future trends in underfill resin will be to have properties of extremely low elastic modulus and non-linear properties such as creep.     

Effect of the plasma cleaning process on plastic ball grid array package assembly reliability

Interface delamination is recognized as one of the major failures of microelectronics packaging. It can result from various factors, including stresses from mismatch of adherent materials, hygrothermal stress from the release of vapor pressure of moisture during soldering reflow process, and interface material adhesion strength. The failure mechanisms are associated with cyclic loads, temperature and moisture condition as well as interface adhesion strength degradation. This paper focuses on the evaluation of plasma cleaning on PBGA assembly, including resistance to interface delamination. Two different plasma systems, powered by radio frequency (RF) and microwave (MW) energy, are studied. The optimized plasma cleaning process parameters are obtained by surface contact angle measurements. The plasma cleaning results are also verified by scanning electron microscopy (SEM) as well as physical pull and shear tests. The test vehicles are 27/spl times/27 mm 292-ball PBGAs. The results from encapsulation peel tests, die and encapsulant pull tests, bonding wire pull tests and C-Mode SAM (C-SAM) examination are presented. It is clear that an optimal plasma cleaning process can be achieved with different plasma systems. The experimental results also demonstrate that plasma cleaning has little effect on wire bonding process and die attach pull strength for given substrates and assembly materials. In all the cases, optimal plasma cleaning steps improve PBGA resistance against interface delaminations for cases where plasma cleaning is carried out before encapsulation process. Moreover, different plasma cleaning techniques would affect the assembly productivity, investment and yield. This paper demonstrates that the optimized plasma cleaning process would enhance PBGA package qualification level and improve the process yields and productivity.     

Evaluation of Cu-bumps with lead-free solders for flip-chip package applications

Low cost electroplated Cu-bump with environmental friendly Sn solder was developed for flip-chip applications. The seed layer used was Ti/WN_x/Ti/Cu where WN_x was used as the Cu diffusion barrier and Ti was used to enhance the adhesion between bump and the chip pad. Thick negative photoresist (THB JSR-151N) with a high aspect ratio of 2.4 was used for electroplating of copper bump and Sn solder. The Sn solder cap was reflowed at 225° for 6 min at N₂ atmosphere. No wetting phenomenon was observed for the Sn solder as evaluated by energy-dispersed spectroscopy (EDS). The Cu-bump with Ti/WN_x/Ti/Cu seed layer not only have higher shear force than the Cu-bump with Ti/Cu seed layer but also has higher resistance to fatigue failure than the Au, SnCu, SnAg bumps.     

The application of flip-chip bonding interconnection technique on the module assembly of 10 Gbps laser diode

Flip chip bonding technique using Pb/In solder bumps was applied to packaging of a 10 Gbps laser diode (LD) submodule for high speed optical communication systems. The effect of the flip-chip bonding interconnection technique instead of conventional wire bonding was investigated for high speed broad band devices. The broad band performance of 10 Gbps LD submodule was simulated using SPICE S/W and compared with experimental results. In this simulation, the 10 Gbps LD was modeled in a parallel RC circuit. The values of R and C used for the equivalent circuit were 5ω and 1 pF, respectively. The LD was placed in series with a 18ω thin film resistor to prevent the impedance mismatch between the LD and a 25ω transmission line. The dependence of parasitic parameters on the small signal modulation bandwidth and the scattering parameters of the LD submodule was investigated and analyzed up to 20 GHz. A small signal modulation bandwidth of 14 GHz at 10 mA dc bias current and the clean modulation response up to 20 GHz were found for the flip-chip bonded submodule. The bandwidth of flip-chip bonded 10 Gbps LD submodule is wider than that of the wire-bonded LD submodule by a difference of 3.8 GHz.     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

Characterization of lead-free solders and under bump metallurgies for flip-chip package

A variety of Pb-free solders and under bump metallurgies (UBMs) was investigated for flip chip packaging applications. The result shows that the Sn-0.7Cu eutectic alloy has the best fatigue life and it possess the most desirable failure mechanism in both thermal and isothermal mechanical tests regardless of UBM type. Although the electroless Ni-P UBM has a much slower reaction rate with solders than the Cu UBM, room temperature mechanical fatigue is worse than on the Cu UBM when coupled with either Sn-3.8Ag-0.7Cu or Sn-3.5Ag solder. The Sn-37Pb solder consumes less Cu UBM than all other Pb-free solders during reflow. However, Sn-37Pb consumes more Cu after solid state annealing. Studies on aging, tensile, and shear mechanical properties show that the Sn-0.7Cu alloy is the most favorable Pb-free solder for flip chip applications. When coupled with underfill encapsulation in a direct chip attach (DCA) test device, the Sn-0.7Cu bump with Cu UBM exhibits a characteristic life or 5322 cycles under -55/spl deg/C/+150/spl deg/C air-to-air thermal cycling condition.     

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

An intrachip wireless interconnect using integrated antennas is demonstrated in a flip-chip ball grid array package. The wireless interconnect consists of a transmitter-receiver pair, which is fabricated in a 0.18-/spl mu/m CMOS process. A 15-GHz signal is generated and broadcasted across the integrated circuit. The signal is picked up by a receiver 4 mm away on the same integrated circuit and frequency divided by eight to produce a 1.875-GHz local clock signal. The interconnection is also demonstrated between a transmitting antenna and a packaged receiver 40 cm away from the transmitting antenna. Demonstration of intrachip wireless interconnects in a package has been considered the ultimate test for this technology.     

Optimal design toward enhancement of thermomechanical reliability of polyimide layers in a flip-chip-on-lead-frame dual flat no-leads package with copper pillar bumps

Thermomechanical reliability of polyimide layers in a flip-chip-on-lead-frame dual flat no-leads package subjected to thermal cycling test condition was studied by the finite element method and the Taguchi method. Different control factors were considered for optimal design toward enhancement of the thermomechanical reliability of polyimide layers, including diameter of the Cu pillar bumps, polyimide opening, and size of the Al pad. Conforming to design rules, the largest Al pad diameter, the smallest size of bump diameter, and the largest polyimide opening were found to be beneficial to enhance the thermomechanical reliability of polyimide layers. And the optimal design was experimentally verified.     

中国及亚太地区的倒装芯片封装技术

在亚太地区的中国和其它国家中,电子封装业和电子装配制造业方面增长的潜力仍然是巨大的。尽管西方国家和日本目前还控制着技术和市场发展的局势,然而通过发展合适的基础设施和制造能力,中国和亚太地区的其它国家将在新世纪内起到重要的作用,通过与各种传统的引线框架的比较,技术上我们对中国和其它亚太国家在开发倒装芯片封装所面的风险,要求及其优点进行了评估,阐述了开发倒装芯片封装技术的指导方针。     

Early experience with in situ chip-to-chip alignment characterization of Proximity Communication flip-chip package

Proximity Communication (PxC) facilitates the integration of VLSI chips in a package using near-field capacitive coupling between chips, eliminating the need for solder or wires for I/O at the chip-to-chip interface. PxC provides chip-to-chip interconnect with bandwidth density and energy per bit similar to on-chip I/O, enabling system on a chip performance within a package. We have built early packages to explore assembly concepts and developed test methods for verification of the PxC design space. This package started with an adhesively-bonded three-chip subassembly of two Island chips and one Bridge chip. The two outer Island chips were reflowed to an alumina ceramic substrate. In the resulting package, communication between chips was achieved using PxC from Island to Bridge and then from the Bridge to the other Island. We demonstrated the ability to detect the X, Y, and Z chip-to-chip relative location and the ability to steer PxC data to optimize signal integrity within the package. This paper describes the first demonstration of active monitoring of chip-to-chip alignment during thermal cycling, in a PxC-enabled package. Leveraging this work, future packages will better exploit PxC benefits such as free-space electrical interconnect and re-workability of multi-chip modules.     

PBGA封装热可靠性分析

对PBGA封装体建立了有限元数值模拟分析模型。模型采用无铅焊点,完全焊点阵列形式。研究了封装体在经历IPC9701标准下的五种不同温度循环加载后,受到的热应力、应变,以及可能的失效形式。结果表明,焊点是封装体结构失效的关键环节,焊点所受应力大小与焊点位置有关。比较了不同温度循环下封装体的疲劳寿命。其结果为提高封装体的可靠性和优化设计提供了理论依据。     

Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.     

Effects of thermoplastic resin content of anisotropic conductive films on the pressure cooker test reliability of anisotropic conductive film flip-chip assembly

The flip-chip technology using anisotropic conductive films (ACFs) is gaining growing interest due to its technical advantages such as environmentally friendly, simpler, and lower cost processes. Electrical performances and reliability of ACF flip-chip assembly depend on thermomechanical properties of ACF polymer resins. In this paper, the changes in ACF resin morphology due to the phase separation of thermoplastics, and subsequent changes of physical and mechanical properties were investigated as a function of thermoplastic contents of ACF formulation. Furthermore, the pressure cooker test (PCT) reliability of ACF flip-chip assemblies with various thermoplastic contents was also investigated. As thermoplastic contents increased, coefficient of thermal expansion (CTE) of ACFs increased, and elastic modulus (E′) of ACFs decreased. In contrast, water absorption rate decreased as thermoplastic content increased. As a result, PCT reliability of ACF flip-chip assembly was improved adding up to 50 wt.% content of thermoplastic. An erratum to this article is available at .