Revisiting power cycling test for better life-time prediction in traction

This paper discusses the commonly accepted method for life-time prediction for power converters in traction. The method is based on junction temperature estimation and thermal cycles on a given duty cycle. The predicted numbers of thermal cycles are compared to the curves giving the number of cycles to failure versus temperature cycles. These curves are extrapolated from power cycling tests. Power cycling tests and extrapolation method will be discussed, particularly under the aspect of failure mechanisms that are induced. In order to generate the same failure mechanisms in power cycling than in the real applications, a new power cycling approach is presented.     

A versatile, via terminated electromigration test structure for various stress modes used during fast wafer level reliability (fWLR) testing

A multipurpose electromigration (EM) test structure designed for advanced fast wafer level reliability (WLR) tests is described in this work. It is shown that different failure location and failure modes can be detected electrically by this test structures which is beneficial for early technology development as well as productive in-line monitoring. Highly accelerated WLR tests use the metal self-heating effect for temperature stress acceleration. It is shown here that the design of interconnects with respect to the critical metal line and the periphery of the tested metal line has a large impact on the stress temperature. A carefully designed test structure guarantees the ability to test for different EM failure modes (upstream, downstream). The presented experimental data focuses on the investigation of different process splits.     

Effects of different test profiles of temperature cycling tests on the reliability of RFID tags

Passive UHF radio-frequency identification (RFID) tags are used for object identification in various environmental conditions, which may affect the reliability of these tags. The effects of different environmental stresses can be studied with accelerated life tests (ALT). Choosing the most suitable test may be challenging: The results are needed as fast as possible, but the failure mechanisms must replicate those occurring in the real operating environment. Here the effects of different temperature cycling profiles were studied by altering temperature ranges, extreme temperatures, soak times to extreme temperatures and transition times between extreme temperatures. Failure times clearly differed between the tests. The test with the fastest transition time and the shortest soak time seemed to have the most acceleration. It was also observed that the different temperature cycling profiles affected the failure mechanisms detected. Cracking of the antenna was observed with lower temperature extremes or shorter soak and transition times. However, with longer soak and transition times, cracks were seen in the RFID interconnections. Both cases led to changes in the impedance matching and consequently to failures. The totally different failure mechanisms clearly demonstrate the importance of carefully determining the test parameters in order to achieve the correct failure mechanism.     

Investigation of low temperature SRAM and ROM failures to enable the replacement of cold test insertion by room temperature test

The replacement of cold test insertion by room temperature test is one possibility of cost reduction. Therefore, a screening concept at room temperature was implemented to address the low temperature failures too. Although, a clever screening concept was able to find most of the low temperature failures, some still could not be caught. To enable the cold test replacement the failure mechanisms of these failures had to be understood. This paper describes the analysis of SRAM and ROM cells failing at low temperature, which could not be detected by this screening concept. It includes the electrical characterisation as well as the physical root cause finding.     

Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect

Electromigration experiments are conducted for submicron dual damascene copper lower level interconnect samples of different stress free temperatures. The electromigration life-time is found to be strongly depend on the stress state of the metallization and the stress gradient that exist due to thermal mismatch of various materials surrounding the copper metallization. It is found that by reducing the stress free temperature, electromigration lifetime can be improved. In order to explain the life-time behavior, an atomic flux divergence based coupled field finite element model is developed. The model predicts a reduction in the atomic flux divergence at the electromigration test condition due to the reduction in the stress free temperature as the key factor responsible for longer electromigration life-time observed experimentally.     

1300 V, 2 ms pulse inductive load switching test circuit with 20 ns selectable crowbar intervention

A non destructive inductive load switching (ILS) test apparatus with the capability of delivering high current pulses with a maximum 2 ms duration under a 1300 V supply is presented in this work. The system is also provided with a fast crowbar whose intervention is programmable with a 20 ns resolution and is intended to perform tests on power devices driving generic inductive loads. This kind of test is commonly used for quality control and prototype verification in power devices industry [Busatto G, Cascone B, Fratelli L, Balsamo M, Iannuzzo F, Velardi F. Non-destructive high temperature characterization of high-voltage IGBTs. Microelectron Reliab 2002;42(9–11):1635–40]. The high resolution crowbar intervention allows an immediate steering of the current away from the Device Under Test (DUT) after the failure event. In this way device damage is minimized so as to have a better understanding of the exact position of the failure, an essential parameter to infer the reasons that caused it [Trivedi M, Shenai K. Failure mechanisms of IGBTs under short-circuit and clamped inductive switching stress. IEEE Trans Power Electron 1999;14(1):108–16; Breglio G, Irace A, Riccio M, Spirito P, Hamada K, Nishijima T, et al. Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. Microelectron Reliab 2008;48(8–9):1432–4].     

Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections. Part 1: Effects of Test Parameters

The work presented in part 1 of this study focuses on identifying the effects of thermal cycling test parameters on the lifetime of ball grid array (BGA) component boards. Detailed understanding about the effects of the thermal cycling parameters is essential because it provides means to develop more efficient and meaningful methods of reliability assessment for electronic products. The study was carried out with a single package type (BGA with 144 solder balls), printed wiring board (eight-layer build-up FR4 structure), and solder interconnection composition (Sn-3.1Ag-0.5Cu) to ensure that individual test results would be comparable with each other. The effects of (i) temperature difference (ΔT), (ii) lower dwell temperature and lower dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate were evaluated. Based on the characteristic lifetimes, the thermal cycling profiles were categorized into three lifetime groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. Thus, one might be tempted to use the highly accelerated conditions to produce lifetime statistics as quickly as possible. However, to do this one needs to know that the failure mechanisms do not change from one lifetime group to another and that the failure mechanisms correlate with real-use failures. Therefore, in part 2 the observed differences in component board lifetimes will be explained by studying the failure mechanisms that take place in the three lifetime groups.     

Power cycling test and failure analysis of molded Intelligent Power IGBT Module under different temperature swing durations

Molded IGBT modules are widely used in low power motor drive applications due to their advantage like compactness, low cost, and high reliability. Thermo-mechanical stress is generally the main cause of degradation of IGBT modules and thus much research has been performed to investigate the effect of temperature stresses on IGBT modules such as temperature swing and steady-state temperature. The temperature swing duration is also an important factor from a real application point of view, but there is a still lack of quantitative study. In this paper, the impact of temperature swing duration on the lifetime of 600 V, 30 A, 3-phase molded Intelligent Power Modules (IPM) and their failure mechanisms are investigated. The study is based on the accelerated power cycling test results of 36 samples under 6 different conditions and tests are performed under realistic electrical conditions by an advanced power cycling test setup. The results show that the temperature swing duration has a significant effect on the lifetime of IGBT modules. Longer temperature swing duration leads to the smaller number of cycles to failure. Further, it also shows that the bond-wire crack is the main failure mechanism of the tested IGBT modules.     

The experimental study for the solder joint reliability of high I/O FCBGAs with thermal loaded bend test

In this study, the reliability of flip-chip ball-grid array package (FCBGA) is explored by a cyclic four-point bend test executed at different controlled temperature. The test vehicle is put in a heated chamber and the resulting daisy chain resistance and strains variations are monitored to check its failure. The strain gauges are mounted near the component corners to get the strains of the test boards when under bending. A data logger records the daisy chain resistance simultaneously during the test. The component failure is detected with a self-written program by judging when the failure resistance of the daisy chain is larger than 20% of its initial resistance. The test results at various temperatures showed that the component life cycle is reduced with the increase of the temperature during the cyclic bend test when under a fixed maximum deflection setting. If tested at room temperature by varying the maximum deflections, the component life cycle is also reduced with the increase of the maximum deflection in the cyclic bend test. Through the fitted curve of all these test data, it is then possible to get relating equations among the variables of temperature, deflection, and life cycle. An extra test is conducted to verify these deduced equations with an error of only 6% approximately. Furthermore, the optic microscope is utilized to observe the failure mode of the FCBGA component after the test. It is found that all the failures are the delamination at the interface of solder balls and substrate. Also, from the results of tested curves, it can be used to predict the component life cycle at elevated temperatures based on the results tested at room temperature.     

Reliability test and failure analysis of high power LED packages

A new type application specific light emitting diode(LED) package(ASLP) with freeform polycarbonate lens for street lighting is developed,whose manufacturing processes are compatible with a typical LED packaging process.The reliability test methods and failure criterions from different vendors are reviewed and compared.It is found that test methods and failure criterions are quite different.The rapid reliability assessment standards are urgently needed for the LED industry.85℃/85 RH with 700 mA is used to test our LED modules with three other vendors for 1000 h,showing no visible degradation in optical performance for our modules,with two other vendors showing significant degradation.Some failure analysis methods such as C-SAM,Nano X-ray CT and optical microscope are used for LED packages.Some failure mechanisms such as delaminations and cracks are detected in the LED packages after the accelerated reliability testing.The finite element simulation method is helpful for the failure analysis and design of the reliability of the LED packaging.One example is used to show one currently used module in industry is vulnerable and may not easily pass the harsh thermal cycle testing.     

基于硅压阻式传感器与光纤传感的静压桩贯入模型试验应用研究

将微型硅压阻式土压力传感器、孔隙水压力传感器及增敏微 型光纤光栅(fiber Bragg grating,FBG)应变传感器应用于静压桩贯入模型试验中,很好地测试了静 压桩贯入过程桩端 阻力、桩身轴力、桩土界面土压力和孔隙水压力。初步试验表明,微型硅压阻式土压力传感 器、孔隙水压 力传感器及增敏微型FBG应变传感器应用在静压模型桩贯入过程中,实现了贯入过程的桩端 阻力、桩身轴 力、桩土界面土压力和孔隙水压力的实时监测;桩身轴力和桩土界面有效侧向压力均随贯入 深度的增加而 增加,但同一深度处侧向压力逐渐减小。为静压桩贯入测试方法提供了参考依据,对进一步 研发室内试验微型传感器具有参考价值。     

AlGaAs/GaAs双异质结激光器退化的研究

观察了室温下工作的DH激光器退化现象,发现在短时间内退化的器件,除阈值升高外尚伴随着微分量子效率下降。对热稳定性良好,并对于较长时间(>250小时)阈值上升率(△J_(th)/J_(th)千小时)小于3％的器件,高温老化证明它们的寿命都能超过万小时量级。     

Cast: An electrical stress test to monitor single bit failures in flash-EEPROM structures

To increase yield and reliability of flash-EEPROM devices, great effort has been devoted to improve the way of monitoring the tunnel oxide quality, both as regards the electrical measurements and the related test structures. The most popular test is an electrical stress to evaluate the charge or the electric field at breakdown on large area or edge intensive capacitors. Although the capacitor test is a fundamental means to evaluate the oxide quality, it can not detect the subtle defects which are responsible for the most likely flash-EEPROM failure mechanisms such as the single bit over-erasure or failure after an electrical stress. To overcome this difficulty the cell array stress test (CAST, patent pending) has been conceived: by means of a suitable test structure it is possible to detect defective cells in a flash-EEPROM array. Correlation with actual flash-EEPROM yield is demonstrated. This test can be used either as a short-loop monitor for process control and improvement or as an end-of-process wafer level screening.     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

基于均匀化激光双面辐照的热力耦合测试方法研究

为了研究以激光为热源开展材料高温力学性能测试的可行性,建立理论模型与数值模型,分析了材料在双面均匀激光光斑加热下的表面及内部温升。结果表明,理想情况下采用均匀化激光双面辐照的加热方式可以在试件加热区域内形成较均匀的温度场。为验证上述结论,建立了光斑匀化度达92%的激光双面辐照热力耦合测试试验平台,并基于相关测试方法获取了传统加热方式难以快速加热的CFRP层合板高温拉伸强度。结果表明,试件在激光加热中心测试区域(10 mm×10 mm)内的温度均匀性良好。试件在均匀化激光双面辐照下可被快速加热至923℃,测试区域内的最大温度波动为6.8%。文中提出的基于均匀化激光双面辐照的热力耦合测试方法相比传统测试方法具有通用性好、温升率高、测试温度高、测试效率高等一系列的优点。该研究可为进一步研制通用型材料/结构高温升率、高温力学性能试验系统提供关键技术支撑。     

Combining vibration test with finite element analysis for the fatigue life estimation of PBGA components

The study develops a methodology that combines the vibration failure test, finite element analysis (FEA), and theoretical formulation for the calculation of the electronic component’s fatigue life under vibration loading. A specially designed plastic ball grid array (PBGA) component with built-in daisy chain circuits is mounted on a printed wiring board (PWB) as the test vehicle for the vibration test. It is then excited by a sinusoidal vibration whose frequency equals the fundamental frequency of the test vehicle and tested until the component fails. Because the solder balls are too small for direct measurement of their stresses, FEA is used for obtaining the stresses instead. Thus, the real displacements in the vibration test are then inputted to the FEA model when performing the stress analysis. Consequently, the stress versus failure cycles (S–N) curve is constructed by correlating both the obtained stresses on the solder balls and the number of failure cycles in the vibration test. Furthermore, the Miner’s rule is applied in calculating the fatigue damage index for those test components when failed. Finally, a formula for the prediction of the component failure cycle is deduced from all these procedures studied. It is also examined later by firstly predicting the fatigue failure cycle of a component and then conducting a vibration test for the same component for the verification purposes. The field test results have proven to be consistent with predicted results. It is then believed that the methodology is effective in predicting component’s life and may be applied further in improving the reliability of electronic systems.     

Advanced power cycler with intelligent monitoring strategy of IGBT module under test

Power cycling (PC) test is one of the important test methods to assess the reliability performance of power device modules related to packaging technology, in respect to temperature stress. In this paper, an advanced power cycler with a real-time V_{CE_ON} and V_F measurement circuit for the IGBT and diode, which for the wear-out condition monitoring are presented. This advanced power cycler allows to perform power cycling test cost-effectively under conditions close to real power converter applications. In addition, an intelligent monitoring strategy for the separation of package-related wear-out failure mechanisms has been proposed. By means of the proposed method, the wear-out failure mechanisms of an IGBT module can be separated without any additional efforts during the power cycling tests. The validity and effectiveness of the proposed monitoring strategy are also verified by experiments.     

Investigation of Arrhenius acceleration factor for integrated circuit early life failure region with several failure mechanisms

Use of the Arrhenius equation for analysis of burn-in and life test data has been called into question in recent years. Validity of the Arrhenius activation energy is asserted to be restricted to only one failure mechanism. Therefore, if multiple failure mechanisms apply to an integrated circuit type, the temperature acceleration factor must be complex. In this study a model is constructed using the Weibull distribution for the failure rate applicable when there are multiple failure mechanisms. In this model a different Arrhenius activation energy corresponds to each failure mechanism. It is shown that under conditions expected to be valid for most integrated circuits, an empirical effective Arrhenius activation energy can be computed that is valid for life test data taken under typical conditions to better than 10%. This provides some justification for the continued usage of a simple Arrhenius equation as an empirical model to analyze life test data.     

A wafer-level approach to device lifetesting

An innovative wafer-level methodology is introduced and used to determine the thermal activation energies of TriQuint semiconductor’s TQPED devices. Activation energies of 2.77 eV and 2.44 eV are calculated for the depletion-mode and enhancement-mode devices, respectively. This accelerated lifetest technique utilizes a special reliability test structure that includes an on-wafer heating element around the device under test (DUT). The heating element easily achieved temperature above 275 °C without the need to bias the device. This allows the exclusive study of thermally activated failure mechanisms. The special reliability test structure allows the stressing of individual devices at different temperatures on the same wafer. This built-in flexibility allows for a fast and efficient means of evaluating device reliability by eliminating packaging overhead and considerations. In wafer form it becomes possible to spatially map the reliability of devices under test. It is also easier to observe the physical degradation of devices and determine the failure mechanisms.     

GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.