Electrical observation of deep traps in high-/spl kappa//metal gate stack transistors

The instability of threshold voltage in high-/spl kappa//metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical.     

High-/spl kappa//metal-gate stack and its MOSFET characteristics

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.     

Modeling of charge trapping induced threshold-voltage instability in high-/spl kappa/ gate dielectric FETs

The authors have developed a distributed tunneling model to investigate the threshold-voltage instability induced by charge trapping in field-effect transistors (FETs) using high-/spl kappa/ gate dielectric materials. The charge trapping dynamics in the high-/spl kappa/ layer are modeled based on a rate equation, which is self-consistently incorporated into device-level simulations. The model is used to simulate pulsed operation of HfO/sub 2/ based n-type FETs; good agreement is obtained with pulsed measurements including the dependence of the threshold-voltage shift on pulse heights and durations. The trap-energy-level shift due to the polaron effect is found to be critical to model the pulse-height dependence of the threshold-voltage shift.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

High work-function metal gate and high-/spl kappa/ dielectrics for charge trap flash memory device applications

We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-/spl kappa/ dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-/spl kappa/) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high /spl Phi//sub M/ gate and high-/spl kappa/ materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.     

A study of relaxation current in high-/spl kappa/ dielectric stacks

Dielectric relaxation currents in SiO/sub 2//Al/sub 2/O/sub 3/ and SiO/sub 2//HfO/sub 2/ high-/spl kappa/ dielectric stacks are studied in this paper. We studied the thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-/spl kappa/ dielectric stacks. It is found that high-/spl kappa/ dielectric stacks show different characteristics than what is expected based on the dielectric material polarization model. By the drain current variation measurement in n-channel MOSFET, we confirm that electron trapping and detrapping in the high-/spl kappa/ dielectric stacks is the cause of the dielectric relaxation current. From substrate injection experiments, it is also concluded that the relaxation current is mainly due to the traps located near the SiO/sub 2//high-/spl kappa/ interface. As the electron trapping induces a serious threshold voltage shift problem, a low trap density at the SiO/sub 2//high-/spl kappa/ interface is a key requirement for high-/spl kappa/ dielectric stack application and reliability in MOS devices.     

Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate

Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric, HfN-TaN metal gate and self-aligned NiGe S/D. The drain drivability is improved over the silicon counterpart with PtSi S/D by as much as /spl sim/5 times due to the lower hole Schottky barrier of the NiGe-Ge contact than that of PtSi-Si contact as well as the higher mobility of Ge channel than that of Si.     

MOS characteristics of substituted Al gate on high-/spl kappa/ dielectric

Substituted aluminum (SA) metal gate on high-/spl kappa/ gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved for a Ti-Al-polysilicon-HfAlON gate structure by a low-temperature annealing at 450/spl deg/C. The SA gate on HfAlON dielectric shows a very low work function of 4.25eV, which is well suitable for bulk nMOSFETs. The SA process is fully free from the Fermi-level pinning problem. In addition, the SA process also shows improved uniformity in leakage current distribution compared to fully silicided metal gate.     

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.     

Improved interface quality and charge-trapping characteristics of MOSFETs with high-/spl kappa/ gate dielectric

The effects of high-pressure annealing on interface properties and charge trapping of nMOSFET with high-/spl kappa/ dielectric were investigated. Comparing with conventional forming gas (H/sub 2//Ar=4%/96%) annealed sample, nMOSFET sample annealed in high-pressure (5-20 atm), pure H/sub 2/ ambient at 400/spl deg/C shows 10%-15% improvements in linear drain current (I/sub d/) and maximum transconductance (g/sub m,max/). Interface trap density and charge trapping properties were characterized with charge pumping measurements and "single pulsed" I/sub d/-V/sub g/ measurements where reduced interface state density and improved charge trapping characteristics were observed after high pressure annealing. These results indicate that high pressure pure hydrogen annealing can be a crucial process for future high-/spl kappa/ gate dielectric applications.     

Device performance of transistors with high-/spl kappa/ dielectrics using cross-wafer-scaled interface-layer thickness

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO/sub 2/ interface layer between a silicon substrate and high-/spl kappa/ dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO/sub 2/ interface. This technique provides a powerful tool in examining the effect of the process variations on device performance.     

Ge n-MOSFETs on lightly doped substrates with high-/spl kappa/ dielectric and TaN gate

In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.     

Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate

In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.     

Characterization of accumulation layer capacitance for extracting data on high-/spl kappa/ gate dielectrics

A new parameter extraction technique has been outlined for high-/spl kappa/ gate dielectrics that directly yields values of the dielectric capacitance C/sub di/, the accumulation layer surface potential quotient, /spl beta//sub acc/, the flat-band voltage, the surface potential /spl phi//sub s/, the dielectric voltage, the channel doping density and the interface charge density at flat-band. The parallel capacitance, C/sub p/(=C/sub sc/+C/sub it/), was found to be an exponential function of /spl phi//sub s/ in the strong accumulation regime, for seven different high-/spl kappa/ gate dielectrics. The slope of the experimental lnC/sub p/(/spl phi//sub s/) plot, i.e., |/spl beta//sub acc/|, was found to depend strongly on the physical properties of the high-/spl kappa/ dielectric, i.e., was inversely proportional to [(/spl phi//sub b/m/sup *//m)/sup 1/2/K/C/sub di/], where /spl phi//sub b/ is the band offset, and m/sup */ is the effective tunneling mass. Extraction of /spl beta//sub acc/ represented an experimental carrier confinement index for the accumulation layer and an experimental gate-dielectric direct-tunneling current index. /spl beta//sub acc/ may also be an effective tool for monitoring the effects of post-deposition annealing/processing.     

Mobility improvement after HCl post-deposition cleaning of high-/spl kappa/ dielectric: a potential issue in wet etching of dual metal gate Process technology

The effect of deionized water and dilute hydrochloric acid, 500:1 (HCl) post-Hf-silicate deposition cleaning on the device characteristics of Hf-silicate MOSFETs have been investigated. The results suggest that a significant improvement in mobility and equivalent oxide thickness scaling can be obtained using HCl post-treatment in comparison to control and H/sub 2/O post-treated devices. The enhancement in bulk trapping immunity has been attributed to the reduced charge trapping in the bulk high-/spl kappa/ layers, whereas no apparent change in interface properties could be observed. The effect of the post-deposition cleaning might have important implications on the wet etching of gate metals in dual-metal-gate technology.     

Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization

A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.     

A novel MONOS-type nonvolatile memory using high-/spl kappa/ dielectrics for improved data retention and programming speed

This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO/sub 2/) as tunneling and blocking layer and tantalum pentoxide (Ta/sub 2/O/sub 5/) as the charge trapping layer. The superiorities of such devices to traditional SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 /spl mu/s and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated.     

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.     

Threshold voltage (V/sub th/) instability in HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate: comparison between NH/sub 3/ and O/sub 3/ interface treatments

The impacts of O/sub 3/ or NH/sub 3/ interface treatments on the long-term V/sub th/ instability in nMOSFET HfO/sub 2/ high-/spl kappa/ gate stacks with TiN metal gate electrodes are compared. The NH/sub 3/ interface treatment is found to be beneficial to suppress the V/sub th/ shift compared to the O/sub 3/-treated samples. This is explained by an enhanced valence band electrons injection in O/sub 3/-treated samples and is experimentally confirmed through a carrier separation measurement. The dynamic stress measurement also indicates that trapped charges are more easily detrapped in NH/sub 3/-treated samples than O/sub 3/-treated samples, improving significantly the V/sub th/ stability.     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.