倒装芯片钉头Au凸点的制作与测试

本文简单回顾了倒装芯片（FC）凸点技术的发展和现状，研究了利用传统的金丝球焊机制作钉头Au凸点（SBB）的工艺，初步完成了在微波GaAs芯片上金凸点的制作，测试了凸点的剪切力和接触电阻，为下一步倒装焊的基础工艺研究打下良好的基础。     

热超声倒装焊在制作大功率GaN基LED中的应用

设计了适合于倒装的大功率GaN基LED芯片结构,在倒装基板硅片上制作了金凸点,采用热超声倒装焊接(FCB)技术将芯片倒装在基板上.测试结果表明获得的大面积金凸点连接的剪切力最高达53.93 g/bump,焊接后的GaN基绿光LED在350 mA工作电流下正向电压为3.0 V.将热超声倒装焊接技术用于制作大功率GaN基LED器件,能起到良好的机械互连和电气互连.     

钉头金凸点芯片用于TAB技术的研究

本文介绍使用超声金丝球焊接机形成的钉头金凸点焊接载带内引线的工艺过程,通过环境应力试验证明该技术可以满足TAB技术中芯片凸点的制作。     

IC芯片钉头金凸点的制作技术研究

重点介绍采用金丝球焊机制作IC芯片钉头形金凸点的工艺技术、钉头金凸点的整平方法及金凸点抗剪切强度的评价.     

微波芯片倒装金凸点热疲劳可靠性分析及优化

为了满足射频系统小型化的需求,提出了一种基于硅基板的微波芯片倒装封装结构,解决了微波芯片倒装背金接地的问题.使用球栅阵列(BGA)封装分布为周边型排列的GaAs微波芯片建立了三维有限元封装模型,研究了微波芯片倒装封装结构在-55～125℃热循环加载下金凸点上的等效总应变分布规律,同时研究了封装尺寸因素对于金凸点可靠性的影响.通过正交试验设计,研究了凸点高度、凸点直径以及焊料片厚度对凸点可靠性的影响程度.结果表明:金凸点离芯片中心越近,其可靠性越差.上述各结构尺寸因素对凸点可靠性影响程度的主次顺序为:焊料片厚度＞金凸点直径＞金凸点高度.因此,在进行微波芯片倒装封装结构设计时,应尽可能选择较薄的共晶焊料片来保证金凸点的热疲劳可靠性.     

金凸点的打球法制作与可靠性考核

本文采用打球法在芯片上制作金凸点，并将凸点倒装焊接在Ti/Ni/Au多层金属化的LTCC基板上。利用扫描电镜观察凸点形貌，X射线透射研究倒装互连状况，并通过接触电阻和剪切强度对凸点倒装焊的可靠性进行了考核。     

倒装焊接在压力敏感芯片封装工艺中的研究

胶粘引丝无法实现硅压力敏感芯片的小型化封装,无引线封装可以解决该问题。倒装焊接具有高密度、无引线和可靠的优点,通过对传统倒装焊接工艺进行适当的更改,倒装焊接可应用于压力敏感芯片的小型化封装。采用静电封接工艺在普通硅压力敏感芯片上制作保护支撑硅基片,在硅压力敏感芯片的焊盘上制作金凸点,调整倒装焊接的工艺顺序和工艺参数,实现了绝压型硅压力敏感芯片的无引线封装,为压力传感器小型化开辟了一条新路。试验结果表明该封装方式可靠性高,寿命长,具有耐恶劣环境的特点。     

用于倒装芯片的晶片凸点制作工艺研究

倒装芯片在电子封装互连中占有越来越多的份额,是一种必然的发展趋势,所以对倒装芯片技术的研究变得非常重要。倒装芯片凸点的形成是其工艺过程的关键。现有的凸点制作方法主要有蒸镀焊料凸点、电镀凸点、微球装配方法、焊料转送、在没有UBM的铅焊盘上做金球凸点、使用金做晶片上的凸点、使用镍一金做晶片的凸点等。每种方法都各有其优缺点,适用于不同的工艺要求。介绍了芯片倒装焊基本的焊球类型、制作方法及各自的特点,总结了凸点制作应注意的问题。     

功率型LED芯片的热超声倒装技术

结合功率型GaN基蓝光LED芯片的电极分布,在硅载体上电镀制作了金凸点,然后通过热超声倒装焊接技术将LED芯片焊接到载体硅片上.结果表明,在合适的热超声参数范围内,焊接后的功率型LED光电特性和出光一致性较好,证明了热超声倒装焊接技术是一种可靠有效的功率型光电子器件互连技术.     

RFID芯片超声倒装封装技术研究

超声倒装是近年来芯片封装领域中快速发展的一种倒装技术,具有连接强度高、接触电阻低、可靠性高、低温下短时完成和成本低的优势,特别适合较少凸点的RFID芯片封装。在镀Ni/Au铜基板上进行了RFID芯片超声倒装焊接实验,金凸点与镀Ni/Au铜基板之间实现了冶金结合,获得了良好的力学与电气性能,满足射频要求。     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension.This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability.     

薄膜基板芯片共晶焊技术研究

共晶焊是微电子组装技术中的一种重要焊接工艺,在混合集成电路中得到了越来越多的应用。文章简要介绍了共晶焊接的原理,分析了影响薄膜基板与芯片共晶焊的各种因素,并且选用Ti/Ni/Au膜系和AuSn焊料,利用工装夹具在真空环境下通入氮、氢保护气体的方法进行薄膜基板芯片共晶焊技术的研究。试验证明:焊接基板金属化Au层厚度1.5μm,焊接压力为2kPa,焊接温度330℃,时间30s可有效地使空洞面积控制在10%以下。并在150℃高温贮存以及-65℃~150℃温度循环后对共晶焊接样品的剪切强度和接触电阻进行了试验。在可靠性试验后,样品的剪切强度满足GJB548B-2005的要求,接触电阻变化率小于5%。     

Ultra-high-density interconnection technology of three-dimensional packaging

The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.     

剪切推球测试条件对Au球焊点推球结果的影响

Au引线键合是电子封装中应用广泛的芯片互连技术,剪切推球测试是评价引线键合球焊点质量和完整性的主要方法之一.利用未热老化和热老化不同时间的Au球键合试样,通过试验和数值模拟研究了推球高度和推球速度对推球值和推球失效界面形貌的影响.     

Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

Assessment of Fluxless Solid Liquid Interdiffusion Bonding by Compressive Force of Au-PbSn and Au-SAC for Flip Chip Packaging

Flip chip packaging faces two primary bonding-process obstacles: flux use and geometry mismatch between die and substrate pad pitch. These obstacles motivated the development of a fluxless bonding method called solid–liquid interdiffusion bonding by compressive force (SLICF). SLICF utilizes a mechanical force to form the bond through solid–liquid interdiffusion with a joint-in-via (JIV) architecture for flip chip packaging. SLICF bonding (also known as thermo-mechanical (TM) bonding) forms an instantaneous bond and eliminates the need for reflow infrastructure. Both Au-PbSn and Au-SAC interconnect systems were studied for the SLICF bonding on the JIV architecture at a 130- $mu{rm m}$ pitch. The morphologies of Au-PbSn and Au-SAC in solid-liquid interdiffusion were studied with their kinetics measured by the Au consumption rate. The SLIFC bonds for Au-PbSn and Au-SAC were compared and assessed by mechanical shear tests and thermomechanical stresses. Au with PbSn was found to perform marginally better due to its joint geometry and slower kinetics.      

基于田口方法的微波组件金丝键合工艺优化

为了提高微波组件金丝键合的可靠性,采用楔形金丝键合工艺进行了金丝互连,通过田口试验方法设计 和试验验证,确定了金丝键合最优化的工艺参数组合。研究结果表明：键合金丝质量的影响因素依次是超声功率、键 合压力和键合时间,优化的工艺参数组合依次为超声功率、键合压力、键合时间,优化的工艺参数组合为超声功率 15、键合压力16、键合时间50;采用优化后的工艺参数进行金丝键合操作,获得了稳定性良好的互连金丝,完全满 足混合集成微波电路金丝键合互连应用的需求。