Rapid thermal annealing of si implanted gaas

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 10¹² to 1 × 10¹⁴/cm². The wafers were encapsulated with Si₃N₄ and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 10¹²/cm² at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 10¹³ an activation energy of 1.7 eV was obtained. For a dose of 4 × 10¹² at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm²/V-s. Mobilities decrease to 4000 at a dose of 1 × 10¹³ and to 2500 cm²/V-s at 1 × 10¹⁴/cm². At doses above 1 × 10¹³ the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.     

Rapid thermal annealing of ion implanted cdte

Rapid thermal annealing of ion implantedn-type CdTe has been investigated. Samples were implanted with 60 keV Ar⁺ and As⁺ ions to a dose of 1 × 10¹⁴ cm⁻² and subjected to anneal sequences of 5-100s at temperatures of 350-650° C. Photoluminescence measurements have indicated that the implantation completely quenches the photoluminescence; however, anneals for only 5s at 350° C are sufficient to recover most of the features of the photoluminescence spectrum to that equivalent of unimplanted material. Luminescence spectral features associated with thermal annealing damage and substitutional As in inferred. Type conversion of the As⁺ implanted layer is observed and it has been shown that good diodes can be made, with the best behaviour resulting from a 5s anneal at 450° C. Research supported by the Natural Sciences and Engineering Research Council of Canada     

Rapid thermal annealing of neutron transmutation doped silicon

Rapid thermal annealing (RTA) of neutron transmutation doped Si wafers is shown to be an alternative to conventional furnace annealing. Measurements of resistivity and deep level transient spectroscopy (DLTS), demonstrated annealing on wafers with diameters up to 75 mm. A 4.5 kW incoherent-light RTA furnace was used. Evidence for crystalline slip was found but this did not appear to affect the results. The slip was more severe for the larger diameter wafers. Some results from a DLTS examination of a partially rapid-thermal-annealed wafer are presented.     

Effects of rapid thermal annealing on nitrided gate oxide grown on 4H-SiC

The electrical characteristics of thermally nitrided gate oxides on n-type 4H-SiC, with and without rapid thermal annealing processes, have been investigated and compared in this paper. The effects of annealing time (isothermal annealing) and annealing temperature (isochronal annealing) on the gate oxide quality have also been systematically investigated. After rapid isothermal and isochronal annealings, there has been a significant increase in positive oxide-charge density and in oxide-breakdown time. A correlation between the density of the positive oxide charge and the oxide breakdown reliability has been established. We proposed that the improvement in the oxide-breakdown reliability, tested at electric field of 11 MV/cm, is attributed to trapping of injected electron by the positive oxide charge and not solely due to reduction of SiC-SiO₂ interface-trap density.     

Fluorine behavior in BF 2 + implanted polysilicon films subjected to rapid thermal annealing

The physical and electrical properties of BF ₂ ⁺ implanted polysilicon films subjected to rapid thermal annealing (RTA) are presented. It is found that the out diffusion ofF and its segregation at polysilicon/silicon oxide interface during RTA are the major causes ofF anomalous migration. Fluorine bubbles were observed in BF ₂ ⁺ implanted samples at doses of 1×10¹⁵ and 5×10¹⁵ cm⁻² after RTA.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Sensitivity analysis of ion implanted silicon wafers after rapid thermal annealing

In this study, we have investigated sensitivities of the ion implanted silicon wafers processed by rapid thermal annealing (RTA), which can reveal the variation of sheet resistance as a function of annealing temperature as well as implantation parameters. All the wafers were sequentially implanted by the arsenic or phosphorous implantations at 40, 80, and 100 keV with the dose level of 10¹⁴ to 2 × 10¹⁶ ions/cm². Rapid thermal annealing was carried out for 10 s by the infrared irradiation at a temperature between 850 and 1150°C in the nitrogen ambient. The activated wafer was characterized by the measurements of the sheet resistance and its uniformity mapping. The values of sensitivities are determined from the curve fitting of the experimental data to the fitting equation of correlation between the sheet resistance and process variables. From the sensitivity values and the deviation of sheet resistance, the optimum process conditions minimizing the effects of straggle in process parameters are obtained. As a result, a strong dependence of the sensitivity on the process variables, especially annealing temperatures and dose levels is also found. From the sensitivity analysis of the 10 s RTA process, the optimum values for the implant dose and annealing temperature are found to be in the range of 10¹⁶ ions/cm² and 1050-1100°C, respectively. The sensitivity analysis of sheet resistance will provide valuable data for accurate activation process, offering a guideline for dose monitoring and calibration of ion implantation process.     

Rapid thermal annealing of zirconia films deposited by spray pyrolysis

Zirconia (8 mol% yttria) (YSZ) amorphous layers were deposited by spray pyrolysis on Si oxidized substrates and crystallized by rapid thermal treatment in a home-made halogen lamps furnace. Uniform films were obtained by depositing up to six layers, followed by the thermal treatment. X-ray analysis showed that the cubic phase is obtained during the initial stage of the annealing process. No significant differences with increasing annealing time nor interaction between the YSZ film and the substrate were observed. Ionic conduction in air, with activation energies comparable to those of bulk YSZ ceramics, was observed. The electrical characteristics of the films make them suitable for microelectronics applications.     

Patterning by rapid thermal annealing of GaAs layers grown on diluted nitride QWs

The structural characterization of hole patterns on GaAs cap layers grown on GaInNAs quantum wells (QWs) created by rapid thermal annealing is shown in this work. The effect of annealing temperature on the hole size, as well as the impact of the ion density present during the growth of the QW on the formation of this hole pattern, is presented. Structural (atomic force, scanning electron and transmission electron microscopy) and optical characterization (cathodoluminescence) of the samples is presented. The structure of the planes forming the walls and base of these holes is proposed.     

Rapid thermal alloyed ohmic contact on inp

The results of a study of the electrical and metallurgical properties of thin metallic layers deposited on InP for use as an ohmic contact are presented. A rapid thermal annealing system was used to alloy AuGe/Ni/Au contacts ton-type ion implanted InP. Rutherford backscattering and contact resistivity measurement were used to evaluate the structural and electrical characteristics of these rapid thermal alloyed thin films. Varying degrees of mixing between the metals and the semiconductor were found depending on the temperature and temperature-time cycle. These results were compared to furnace and graphite strip-heater alloying techniques. A correlation between the interface structure and the contact resistance was found. Temperatures between 430 and 450° C and alloying time of 2 sec have produced the best electrical results, with specific contact resistance as low as 2*10^?7 Ω cm² on semi-insulating InP which was Siimplanted with a peak concentration about 2*10¹⁸ cm^?3. The optimum alloy temperature is marked by the onset of substantial wrinkling of the contact surface, whereas essentially smooth surfaces are obtained at temperatures below optimum. The depth of the alloyed ohmic contact is controlled by the time of heating and could be less than 1000Å.     

Rapid Thermal annealing of si implanted GaAs

Rapid thermal annealing (RTA) with incoherent light from tungsten lamps shows high potential relative to the conventional furnace annealing (FA) to activate the implanted dopant. Due to the short time annealing, it could completely eliminate the re-diffusion of dopant and host atom. For the Si implantation with dose of 2 × 10¹⁴ cm², the electrical activity of 78% for RTA was higher than that of the FA. But for this short time, some defects measured by deep level transient spectroscopy (DLTS) were hard to remove. A two-step annealing was suggested by the combination of high temperature RTA (1000° C) and FA (700° C). After the post-FA, the defects would be removed to a great extent, and the electrical activity of dopant also increased. With the dose of 2 x 1013 cm^-2, the activity attained after the two step annealing was 92.5%, which may be the highest value according to our knowledge for rapid thermal annealing on Si ion implanted GaAs.     

Design of Rapid Thermal Processing for Large Diameter Wafer

The relationship between the arrangement of tungsten-halogen lamps and the uniformity of irradiance received by the wafer is discussed, and a sort of axial-symmetrical lamps-array is designed to guarantee that the irradiation on the edge is approximately the same as the one on the center of the wafer. The magnitude of temperature on the wafer vs. the power of tungsten-halogen lamps is calculated numerically.     

Rapid thermal annealing of dual Si and P implants in InP

In this study we evaluate the effects of dual implantation with different doses of Si and P on dopant activation efficiency and carrier mobility in InP:Fe. The implants were activated by a rapid thermal annealing step carried out in an optimized phosphoruscontaining ambient. For high dose implants (10¹⁴–10¹⁵ cm⁻²), which are typically employed for source/drain regions in FETs, dual implantation of equal doses of Si and P results in a higher sheet carrier concentration and lower sheet resistance. For 10¹⁴ cm⁻² Si implants at 150 keV, the optimal P co-implant dose is equal to the Si dose for most anneal temperatures. We obtain an activation efficiency of ∼70% for dual implanted samples annealed at 850° C for 10 sec. The high activation efficiencies and low sheet resistances obtained in this study emphasize the importance of stoichiometry control through the use of P co-implants and a phosphorus-containing ambient during the thermal processing of InP.     

Activation of nitrogen implants in 6H-SiC

We have studied the effect of anneal time and temperature on activation of high-dose nitrogen implants into 6H-SiC. At a fixed anneal temperature, a strong dependence on anneal time is seen. For short anneals, the resistivity initially decreases with anneal time. After a minimum resistivity is reached, resistivity increases with further anneal. The optimum anneal time for minimum resistiv-ity increases as anneal temperature is reduced. Successful activation has been achieved at temperatures as low as 900°C.     

Rapid thermal annealing of magnesium implanted GaAs-GaAIAs heterostructures experimental and simulated distributions

The use of rapid thermal annealing (RTA) techniques to anneal ion implanted GaAs compounds is expected to have a significant impact on device technology. Due to the short duration of the heat treatment, the implanted impurities may be activated without significant diffusion. For heterojunction bipolar transistor (HBT) applications, high doses of p-type impurities are required to compensate the doping levels of N-GaAlAs emitter and n⁺ GaAs contact layers. Multi-implantations were chosen to maintain a flat profile down to the base layer. Energies of 30, 60, 150, and 340 keV with doses of 6 × 10¹³, 9 × 10¹³,6 × 10¹⁴, and 9 × 10¹⁴ cm⁻², respectively, have been used. Annealing cycles with time durations of a few seconds and temperature in the range of 850–950°C are described. Electrical properties of the annealed samples have been investigated using an electrochemical measurement technique. It was found that hole concentrations as high as 4 × 10¹⁹ cm⁻³ and electrical activities near to 75 percent can be obtained. There is no evident indiffusion and no significant outdiffusion at the optimal annealing conditions. Simulation of multilayer implantations are also carried out by an accurate model available in TITAN 2D process simulator using Pearson IV laws and taking into account the diffusion effects on profile distribution caused by RTA. A first approximation using a simple model allows a rapid evaluation of the data fitting operation. In a second approach, concentration dependent diffusivity and the contribution of the electric field at the interface are covered to perform an improved data fitting of ion implanted and annealed dopant profiles. A comparative study shows a good agreement between experimental and simulated distributions.     

Modelling of rapid thermal processing

An overview is given of modelling issues in rapid thermal processing. Firstly, the influence of surface and bulk properties on wafer emissivity is discussed. Secondly, the influence of back-side layers, wafer transparency and back-side roughness on temperature measurement is discussed. Thirdly, several causes of temperature non-uniformity are mentioned.     

Multi-step rapid thermal annealing of boron and indium implanted Hg1−xCdxTe

In this work, we are reporting the use of a two-step rapid thermal annealing (RTA) process (250°C, 100s+340°C, 30s) for the annealing of Hg_1−xCd_xTe (MCT) implanted layers over p-type (x=0.22) substrates. We report a high value of electrical activation (70%) of the indium implants after this short RTA treatment in inert Ar atmosphere. The need of two RTA steps in the annealing recipe is shown, and so the role played by each of them: the first step annihilates the implantation damage, while the second one produces the impurity electrical activation. However, for the boron case, no electrical activity was found after several annealing processes, behaving as an inert species for the case of this bulk MCT material. We also point out the change on the substrate electrical characteristics induced by the thermal treatments, and report the convenience of a subsequent low temperature furnace annealing (200°C, 72 h) to reduce back the bulk carrier concentration to values low enough to achieve an n⁺-p IR detector structure.     

A deep level transient spectroscopy study of rapid thermal annealed arsenic implanted silicon

Deep level traps are observed in silicon that has been implanted with high doses of arsenic and subsequently annealed by rapid thermal annealing. The doses studied create enough damage to form a surface amorphous layer. Annealing temperatures, implant fluence, and the presence of a surface amorphous layer contribute to the type of trap observed. These results show evidence for a clustering/declustering mechanism of arsenic in silicon during rapid thermal annealing.     

Rapid thermal annealing of cerium dioxide thin films sputtered onto silicon (111) substrates: Influence of heating rate on microstructure and electrical properties

The impact of the heating rate (HR) of a Rapid Thermal Annealing (RTA) on the crystallinity and on the morphology of CeO₂ thin films has been investigated by Raman Spectroscopy (RS), Photoluminescence (PL), Scanning Electron Microscopy (SEM), Energy Dispersive Spectroscopy (EDS), and tapping mode Atomic Force Microscopy (AFM). The electrical properties of CeO₂ thin films have also been studied with the Conductive AFM mode. This paper highlights the importance of the heating rate value used during an RTA on crystalline quality, morphology and on the electrical properties of the CeO₂ layer. In fact, the best crystallinity with a good morphology and a high resistivity has been obtained for a CeO₂ layer sputtered on (111) Si substrate and post-annealed at 1000 °C for 30 s with an HR of 25 °C/s.     

Effect of annealing process on the surface roughness in multiple Al implanted 4H-SiC

A P-layer can be formed on a SiC wafer surface by using multiple Al ion implantations and post-implantation annealing in a low pressure CVD reactor.The Al depth profile was almost box shaped with a height of 1×10¹⁹cm^-3 and a depth of 550 nm.Three different annealing processes were developed to protect the wafer surface.Variations in RMS roughness have been measured and compared with each other.The implanted SiC, annealed with a carbon cap,maintains a high-quality surface with an RMS roughness as low as 3.8 nm.Macrosteps and terraces were found in the SiC surface,which annealed by the other two processes（protect in Ar/protect with SiC capped wafer in Ar）.The RMS roughness is 12.2 nm and 6.6 nm,respectively.