Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1.5 V supply voltage, 20 MHz clock frequency, and less than 0.1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feed through errors from switches cancel out. The MOS current mode S/H circuit is designed and simulated using CMOS 0.6 m device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0.1%, and 1 MHz input from a 1.5 V power supply is achievable.     

A 1 V Second Order Sigma-Delta Modulator

A second order switched capacitor sigma-delta modulator operating at a supplyvoltage of 1 V is presented. This low supply voltage restricts the gate overdrivevoltage available for switching transistors. The design relies on the elimination ofcritical switches by using a modified switched op amp for the integrator and novelswitched half-supply and reference voltage generators. The design has been carried outin a fully differential configuration in order to minimize errors arising from chargeinjection and clock-feedthrough effects. The converter has been implemented using aconventional 0.8 m double-poly double-metal CMOS process, having a nominalthreshold voltage of 0.75 V. Test results, showing more than 9 bits of resolutionwith an oversampling ratio of 64, are also presented.     

Design and implementation of a 0.8 V input, 84% duty cycle, variable frequency step-up converter

A 0.8 V input, 84% duty cycle, variable frequency CMOS DC-DC step-up converter with integrated power switches has been presented in this paper. The converter has the properties of both the current mode and hysteric control mode operations. The inductor charging time of the topology is designed to be inversely proportional to the input voltage and as a result the inductor current disturbance dies out immediately. Hence, no external components and extra I/O pins are required for the compensation of the current loop. The step-up converter has been fabricated with a standard pseudo BiCMOS process. Special MOS device of threshold voltage 0.5 V and start-up circuitries enable the converter to start from a voltage as low as 0.8 V. The real time data show that the converter can boost 0.8 V to as high as 5 V, which makes it suitable for low voltage applications. The efficiency of the chip has been found over 75 % for the entire load range from 10 to 100 mA.     

A simple switched-capacitor-based capacitance-to-frequency converter

A simple integrated capacitance-to-frequency converter is presented. Its core is a switched-capacitor integrator. Under the control of a switch clock the converter produces a square-wave signal whose frequency depends on an external capacitor. It is insensitive to parasitic capacitance and not affected by the op amp offset voltage. Moreover, this converter has a linear capacitance-to-frequency transform characteristic. This experimental circuit has been implemented by a low voltage double-polysilicon 5-m NMOS technology. Since the circuit is cost-effective and power consumption is low (less than 10 mW), such a converter is suitable for many mesurement systems which use a capacitor as a sensor. For example, it can be used for atmospheric pressure measurement in a meteorological balloon which cannot be reclaimed after release.     

A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels

A single-inductor step-up DC-DC switching converter with bipolar outputs is implemented for active-matrix OLED mobile display panels. The positive output voltage is regulated by a boost operation with a modified comparator control (MCC), and the negative output voltage is regulated by a charge-pump operation with a proportional-integral (PI) control. The proposed adaptive current-sensing technique successfully supports the implementation of the proposed converter topology and enables the converter to work in both discontinuous-conduction mode (DCM) and continuous-conduction mode (CCM). In addition, with the MCC method, the converter can guarantee a positive output voltage that has both a fast transient response of the comparator control and a small output voltage ripple of the PWM control. A 4.1 mm$^{2}$ converter IC fabricated in a 0.5 $mu$m power BiCMOS process operates at a switching frequency of 1 MHz with a maximum efficiency of 82.3% at an output power of 330 mW.      

A high-efficiency DC-DC buck converter for sub-2×VDD power supply

This paper presents a DC-DC step-down converter, which can accommodate the range of power supply voltage from VDD to sub-2×VDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area of the proposed design is less than 0.184 mm², while the power supply range is up to 5 V. Since the internal reference voltage is 1.0 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a SOC (system-on-chip) to provide multiple supply voltage sources.     

Ultrafast Tracking Power Supply With Fourth-Order Output Filter and Fixed-Frequency Hysteretic Control

A practical solution is presented for the design of a non-isolated dc/dc power converter with very low output ripple voltage and very fast output voltage step response. The converter is intended for use as an envelope tracking power supply for a radio frequency power amplifier (RFPA) in a TETRA enhanced data service (TEDS) base station. A simple and effective fixed-frequency hysteretic control scheme for the converter (buck with fourth-order output filter) is developed and analyzed. The proposed approach is verified experimentally by a 500 W output prototype, capable of delivering any voltage in the range of 10–30 V within 10 $mu{hbox {s}}$ with 10 mVpp of output ripple and efficiencies in the 88%–95% range.      

Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique

In this paper, an integrated adaptive-output switching converter is proposed. The design employs a one-cycle control for fast line regulation and a single outer loop for tight load regulation and fine tuning. A switched-capacitor integrator is introduced to the one-cycle control to obtain positive integration with a single positive power supply, allowing a standard low-cost CMOS fabrication process. To improve the efficiency, a dynamic loss control technique is presented. The converter was designed and fabricated with 0.35 $mu{hbox{m}}$ N-well CMOS process. With a supply voltage of 3 V, a voltage ripple of less than $pm$20 mV is measured. The maximum efficiency is 92% with a load power of 475 mW. The converter exhibits a tracking speed of 23.75 $mu{hbox{s/V}}$ for both start-up and reference voltage transitions. The recovery time for a 20% load change is approximately 9.5 $mu{hbox{s}}$.      

An Integrated Switching DC–DC Converter With Dual-Mode Pulse-Train/PWM Control

This brief presents an integrated switching converter with a dual-mode control scheme. A pulse-train (PT) control employing a combination of four pulse control patterns is proposed to achieve optimal regulation performance under various operation scenarios. Meanwhile, a high-frequency pulsewidth modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling in steady state. The converter was fabricated with a 0.35- $muhbox{m}$ digital CMOS n-well process. The entire die area, including the on-chip pads and power devices, is 1.31 $hbox{mm}^{2}$ . Experimental results show that, in the steady state, the output voltage is well regulated at 1.5 V with $pm$12.5-mV ripples in the PWM mode. The measured maximum efficiency is 91%, and the efficiency stays above 70% within the entire 500-mW power range. In transient measurements, with a 100% load step change from 50 to 100 mA, the output voltage of the converter settles within 345 ns due to the fast response of the PT control, with a maximum voltage variation of 164 mV. The converter functions well when the input supply voltage frequently varies between 2.2 and 3.3 V, with a line regulation of 29.1 mV/V.      

Designing an Adjustable Wide Range Regulated Current Source

LLC resonant converter has been used widely as dc–dc converter for achieving constant dc voltage. In this paper, an LLC resonant converter, by adding an inductance to its conventional topology and considering the rectifying stage stray inductances, is proposed for an adjustable wide range regulated current source (20–200 ${rm A}_{rm dc}$) for using as ion implanter's filament power supply. The additional inductor increases output current adjustment range and efficiency, especially at light loads. Transformer's leakage inductances and rectifying stage stray inductances have been considered. Because of these inductances, the rectifier stage always works in continuous conduction mode, and its conduction angle is forced to be larger than $pi$, and peak current of the rectifier stage and the output capacitor have been reduced effectively. Switching losses and electromagnetic interference noises have been reduced as well due to zero-voltage switching at the primary and secondary sides of the converter, and zero-current switching at its secondary side. Soft switching is achieved for all power devices under all operating conditions. A developed prototype of the converter has been tested under different load (2.5–12.5 m$Omega$) and input voltage conditions (320–370 $V_{rm dc}$) with maximum efficiency of 87%. Experimental results confirm high performance of the designed adjustable and regulated current source even under the worst-case conditions.      

Optimum Design Consideration and Implementation of a Novel Synchronous Rectified Soft-Switched Phase-Shift Full-Bridge Converter for Low-Output-Voltage High-Output-Current Applications

Optimum design consideration and implementation of a novel synchronous rectified soft-switched phase-shift full-bridge dc/dc converter with a primary-side energy storage inductor for server adapter application is presented in this paper. By employing a primary-side energy storage inductor, the main switches can achieve a soft-switching condition, and there is little reverse recovery loss in the body diodes of a secondary-side rectifier due to relatively slow downslope of the triangular current. Since the output capacitive filter reduces the voltage stress across the rectifiers, the synchronous rectifier with a lower breakdown voltage rate can be utilized to improve the conversion efficiency dramatically. Thus, this converter can obtain relatively high conversion efficiency for some medium-power applications with low output voltage and high output current, such as the server adapter. Several key optimum design considerations of this converter are also presented in detail in this paper. Finally, a 100-kHz, 300-W (12$,$V/25$,$ A) laboratory-made prototype for a given server adapter application is built up based on the proposed optimum design procedure of this converter to verify all the theoretical analysis and evaluations.      

Optimization of the parameters of power sources excited by β-radiation

The experimental results and calculations of the efficiency of the energy conversion of Ni-63 β-radiation sources to electricity using silicon p–i–n diodes are presented. All calculations are performed taking into account the energy distribution of β-electrons. An expression for the converter open-circuit voltage is derived taking into account the distribution of high-energy electrons in the space-charge region of the p–i–n diode. Ways of optimizing the converter parameters by improving the technology of diodes and optimizing the emitter active layer and i-region thicknesses of the semiconductor converter are shown. The distribution of the conversion losses to the source and radiation detector and the losses to high-energy electron entry into the semiconductor is calculated. Experimental values of the conversion efficiency of 0.4–0.7% are in good agreement with the calculated parameters.     

A Synchronous Multioutput Step-Up/Down DC–DC Converter With Return Current Control

This brief presents a new return-current control method for a multioutput step-up/down dc–dc converter. Compared with prior multioutput dc–dc converters, the presently described converter can generate outputs higher or lower than the input voltage with simple control-loop compensation while guaranteeing stability in a wide load range. Using a 0.5-$muhbox{m}$ bipolar CMOS (BiCMOS) process, a converter having five outputs has been implemented for an LG active-matrix organic light-emitting diode (AM-OLED) display panel. The implemented converter operates at 1-MHz switching frequency with 4.7- $muhbox{H}$ inductor and 10- $muhbox{F}$ capacitor. Experimental results show that the proposed control method can generate tightly regulated stepped-up or -down outputs stably under a wide load variation. The conversion efficiency is higher than 80% at a typical AM-OLED panel grey level.      

Component-Efficient Multiphase Switched-Capacitor DC–DC Converter With Configurable Conversion Ratios for LCD Driver Applications

A CMOS 3/4-phase switched capacitor dc-dc converter with configurable conversion ratios of $4times/5times/6times/7times$ is proposed for liquid crystal display driver applications. The 3/4-phase driving scheme requires only 3 off-chip flying capacitors and 5 package pins. The converter core, input voltage monitor, 3/4-phase clock generator and bandgap voltage reference were integrated using a 0.35- $mu$m high-voltage CMOS process. The input voltage ranges from 2.5 to 5 V, and the output voltage is higher than 15 V with a load current of 500 $mu$A. Measurement results confirmed the validity and performance of the driving scheme.      

The design of A/D converters using two-range comparators

In this paper, a new architecture for performing analog-to-digital conversion with the throughput of flash conversion, but with some relief from the high power and area requirements, is presented. The key element of this technique is the two-range comparator circuit. This new circuit compares the analog input with more than one reference voltage simultaneously, allowing for a large reduction in the total number of comparator circuits required. Simulation results are presented which show a performance increase of 20% in a converter implemented with the new comparator when compared to a conventional flash converter operated at the same power dissipation level.     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35$ mu{hbox {m}}$ standard CMOS process and tested at 1$~$V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60$~$ dB, input referred noise of 2.5$ muhbox{V}_{rm rms}$ in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.      

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

A Buck-Derived Topology With Improved Step-Down Transient Performance

The slew rate of the inductor current is limited by the inductance value and the voltage across the inductor. In a buck converter, when the controller is saturated, the voltage across the inductor during a step-up load transient is $V_{rm in}-V_{rm out}$, while during a step-down load transient, it is $-V_{rm out}$. Thus, a buck converter with a large conversion ratio offers asymmetrical step-up and step-down transients. Since the rate of fall of the inductor current is much slower than the rate of rise of the inductor current, the step-down transient lasts longer than the step-up transient for the same change in the load current. The step-down slew rate can be increased by reducing the inductance, but it results in higher inductor current ripple, and hence, higher losses in the power converters. In this paper, we present a novel topology for improving the step-down load transients without reducing the inductance value. The scheme operates only during load transients and restores to the normal operating conditions during steady-state operation. It provides reduced voltage overshoots and faster settling times in output voltage during such transients. The proposed scheme is tested on a 1-V/12-A buck converter switching at 1 MHz, and the experimental results are presented.