High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

A high-performance polysilicon thin-film transistor using XeClexcimer laser crystallization of pre-patterned amorphous Si films

A high-performance polysilicon thin-film transistor (TFT) fabricated using XeCl excimer laser crystallization of pre-patterned amorphous Si films is presented. The enhanced TFT performance over previous reported results is attributed to pre-patterning before laser crystallization leading to enhanced lateral grain growth. Device performance has been systematically investigated as a function of the laser energy density, the repetition rate, and the number of laser shots. Under the optimal laser energy density, poly-Si TFT's fabricated using a simple low- temperature (⩽600°C) process have field-effect mobilities of 91 cm²/V·s (electrons) and 55 cm²/V·s (holes), and ON/OFF current ratios over 10 ⁷ at V_Ds=10 V. The excellent overall TFT performance is achieved without substrate heating during laser crystallization and without hydrogenation. The results also show that poly-Si TFT performance is not sensitive to the laser repetition rate and the number of laser shots above 10     

Low-temperature polysilicon thin-film transistors fabricated fromlaser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300°C, and produces devices with mobilities up to 450 cm²/Vs, on/off current ratios greater than 10⁷ , without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films     

Ageing of laser crystallized and unhydrogenated polysilicon thin film transistors

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and then laser crystallized using a single shot ECL (SSECL of SOPRA) with very large excimer laser. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine or diborane to fabricate n-type or p-type transistors respectively.These laser crystallized TFT's show poorer reliability properties than solid-phase crystallized TFT's. This poor stability is explained to originate from the high surface roughness produced by the laser crystallization, which is highlighted from Atomic Force Microscopy observations.Moreover to this conclusion, the behaviour of the threshold voltage shift ΔV_T during positive and negative stresses is checked to the light of a stretched exponential law that is, as supposed, a federative law. This law is explained in hydrogenated amorphous silicon TFT's by a dispersive diffusion coefficient of hydrogen in the disordered material. Taking into account that such relation appears as sufficiently general and, particularly, can describe the behaviour of monocrystalline silicon MOSFET and un-hydrogenated polysilicon TFT's where the hydrogen cannot involved, it can be supposed that it deals with disordered materials and disordered regions in crystalline materials (interface, grain boundary, …..).     

Gate bias stress in hydrogenated and unhydrogenated polysilicon thin film transistors

Polysilicon Thin Film Transistors (TFT's), fabricated at temperature lower than 600°C, are now largely used in many applications, particularly in large area electronics. The reliability of these TFT's under different electrical conditions is then questionable. In this work, Gate bias stress is studied in two types of polysilicon TFT's originated from the same process. One type is unhydrogenated and the other is submitted to a Radio-Frequency hydrogen plasma. As this hydrogenation step is known to improve the TFT's performances but to introduce unstability, the unhydrogenated TFT's are expected to be more stable. The behaviours of the two types of TFT's under the gate bias stress are found however only different. The bias aging of unhydrogenated TFT's fit with the known model of the n-channel c-Si MOSFET's bias stress. The behaviour of the hydrogenated TFT's is explained from the model of defect creation in hydrogenated amorphous silicon.     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Self-aligned aluminum top-gate polysilicon thin-film transistorsfabricated using laser recrystallization and gas-immersion laser doping

We present electrical results from polysilicon thin film transistors (TFT's) fabricated using laser-recrystallized channels and gas-immersion laser-doped source-drain regions. A simple, four-level self-aligned aluminum top-gate process is developed to demonstrate the effectiveness of these laser processes in producing TFT's. The source-drain doping process results in source-drain sheet resistances well below 100 Ω/□. TFT field-effect mobilities in excess of 200 cm²/Vs are measured for the laser-fabricated unhydrogenated TFT's     

The effects of fluorine passivation on polysilicon thin-filmtransistors

The fluorine implantation on polysilicon was found to improve the characteristics of polysilicon thin-film transistors (TFT's). The fluorine passivates the trap states within the polysilicon channel, as compared with the H₂-plasma passivation. The fluorine implantation passivates more uniformly both the band tail-states and midgap deep-state, while the H₂-plasma treatment is more effective to passivate deep states than tail states. A fluorine-implanted device can be further improved its performance if an H₂-plasma treatment is applied. In contrast to the H₂ -plasma passivation, the fluorine passivation improves the device hot-carrier immunity. Combining the fluorine passivation and H₂ -plasma passivation, a high performance TFT with a high hot-carrier immunity can be obtained     

A vertical submicron polysilicon thin-film transistor using a lowtemperature process

This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (⩽600°C). The channel length is determined by the thickness of an SiO₂ film. As a result, submicron vertical polysilicon TFT's can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation     

Influence of rapid thermal and low temperature processing on theelectrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465°C. For the Si films annealed at 750°C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at λ=405 nm), the potential barrier height Φ_B due to the grains, and the field-effect mobility, μ_n,p, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called “grains” of the films annealed at 600°C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance     

A comparison of hydrogen and deuterium plasma treatment effects onpolysilicon TFT performance and dc reliability

We compare the performance and dc reliability of conventional top-gate, self-aligned polysilicon (poly-Si) thin-film transistors (TFT's) after passivation by plasma deuteration and conventional plasma hydrogenation. An optimum deuteration temperature of 300°C is found, as compared to 350°C for hydrogenation. Deuteration yields comparable TFT performance as hydrogenation, while deuterated TFT's exhibit increased resistance to threshold voltage degradation under dc stress. These results indicate that deuteration is a promising alternative to hydrogenation for achieving high-performance, high-reliability poly-Si TFT's for applications such as flat-panel displays     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Performance improvement obtained for thin-film transistorsfabricated in prepatterned laser-recrystallized polysilicon

Thin-film transistors (TFT's) are fabricated in polysilicon films that are laser recrystallized either before or after active-area definition. We find the the performance of TPT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved. For example, the field-effect mobility is increased by a factor of three, the threshold voltage is reduced from 5.32 V to 0.07 V, and the subthreshold slope is cut in half for W/L = 10 μm/10 μm TFT's. All TFT's discussed utilize gas-immersion laser-doped source and drain junctions and are unhydrogenated     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

A novel offset gated polysilicon thin film transistor without anadditional offset mask

We have proposed a novel offset gated polysilicon TFT fabricated without an offset mask in order to reduce leakage current and suppress the kink effect. The photolithographic process steps of the new TFT device are identical to those of conventional non-offset structure TFT's and an additional mask to fabricate an offset structure is not required in our device. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The novel TFT also exhibits a considerable reduction in the kink effect because a very thin film TFT may be easily fabricated due to the elimination of the contact over-etch problem     

The electrostatic charging damage on the characteristics andreliability of polysilicon thin-film transistors during plasmahydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFT's) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFT's with different area of antennas were used to study the damages caused by electrostatic field     

Optimization of silicon-germanium TFT's through the control ofamorphous precursor characteristics

Polycrystalline thin-film transistors (TFT's) are promising for use as high-performance pixel and integrated driver transistors for active matrix liquid crystal displays (AMLCD's). Silicon-germanium is a promising candidate for use as the channel material due to its low thermal budget requirements. The binary nature of the silicon-germanium system complicates the optimization of the channel deposition conditions. To date, little work has been done to perform this optimization, resulting in poor performance for SiGe TFT's. We report on optimization studies done on the low-pressure chemical vapor deposition of SiGe and its effect on TFT performance. We detail the results of a response surface characterization of SiGe deposition, and explain the obtained results in terms of atomistic models of deposition. Optimization strategies to enable the fabrication of high-performance SiGe TFT's are explained, Using these strategies, SiGe TFT's fabricated using solid phase crystallization and a 550°C process are demonstrated, with mobility greater than 40 cm²/V-s. Analysis is also performed on the effect of Ge-catalysis on the maximum optimization range. Results suggest that SiGe may offer enhanced optimization ranges over Si, as a result of this catalysis     

Polycrystalline silicon-germanium thin-film transistors

The fabrication of p- and n-channel MOS thin-film transistors (TFT's) in polycrystalline silicon-germanium (poly-Si_1-xGe _x) films is described, and their electrical characteristics are presented. Various technological issues are then addressed in order to provide direction for further work in optimizing the fabrication process. The initial devices fabricated in this work exhibit well behaved electrical characteristics; enhanced performance is expected to accompany improvements in the crystallization and defect-passivation processes. Compared to a poly-Si TFT technology, an optimized poly-Si _1-xGe_x TFT technology may ultimately be able to provide a lower-temperature, shorter-time processing capability at little expense to device performance and it is therefore promising for large-area electronics applications     

A strategy for modeling of variations due to grain size inpolycrystalline thin-film transistors

A strategy is presented for modeling of performance variation in polycrystalline thin-film transistors (TFT's) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFT's results in reasonable agreement     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm