Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

High‐mobility oxide TFT for circuit integration of AMOLEDs

Abstract— A high‐mobility and high‐reliability oxide thin‐film transistor (TFT) that uses In‐Sn‐Zn‐O (ITZO) as a channel material has been developed. The mobility was 30.9 cm²/V‐sec and the threshold voltage shift after 20,000 sec of a bias‐temperature‐stress (BTS) test (with a stress condition of Vg = 15 V, Vd = 15 V, and T = 50°C) was smaller than 0.1 V. In addition, a method of obtaining a stable enhancement‐type TFT, which realizes circuit integration for active‐matrix organic light‐emitting diode (AMOLED) displays has been developed.     

Oxide‐TFT technologies for next‐generation AMOLED displays

Abstract— High‐mobility high‐reliability low‐RC‐delay oxide TFTs have been developed. Their performances are good enough for AMOLED displays even for the large‐sized super‐high‐resolution, or high‐frame‐rate displays. In this paper, the status of oxide‐TFT development and the issues for the mass‐production of next‐generation AMOLED displays will be discussed, and three types of AMOLED displays using different oxide materials and TFT structures will be demonstrated.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Letter: Mechanisms for on/off currents in dual‐gate a‐Si:H thin‐film transistors using indium‐tin‐oxide top‐gate electrodes

Abstract— Two types of dual‐gate a‐Si:H TFTs were made with transparent indium‐tin‐oxide (ITO) top‐gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on‐currents of these dual‐gate TFTs with dual‐gate driving are due to the high resistance of the parasitic intrinsic a‐Si:H regions between the back electron channel and the source/drain contact. In the off‐state of the dual‐gate‐driven TFTs, the Poole‐Frenkel effect is also enhanced due to back‐channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual‐gate‐driven a‐Si:H TFTs exhibit extremely low photo‐leakage currents, much lower than that of single‐gate‐driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual‐gate TFTs suitable devices for use as switching elements in liquid‐crystal displays (LCDs) or for other applications.     

Impact of source/drain contacts formation of self‐aligned amorphous‐IGZO TFTs on their negative‐bias‐illumination‐stress stabilities

In this study, we have compared the performance of self‐aligned a‐IGZO thin‐film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiN_x interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field‐effect mobility (μ_FE) of over 10.0 cm²/(V.s), sub‐threshold slope (SS^‐1) of 0.5 V/decade, and current ratio (I_ON/I_OFF) over 10⁸. However, under negative‐bias‐illumination‐stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma‐treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel.     

Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².     

Integrated a‐Si TFT row driver circuits for high‐resolution applications

Abstract— A 12.1‐in. tablet liquid‐crystal‐display (LCD) panel with integrated amorphous‐silicon row driver circuits has been developed using a standard TFT process and Advanced Fringe‐Field Switching (AFFS) technology. An XGA‐resolution 768‐stage shift‐register circuit with two‐phase clocks has been designed and fabricated. The circuit parameters were optimized in order to obtain a highly reliable a‐Si row‐driver‐circuit structure. Thermal Humidity Operation (THO) test results at 50°C and 80% humidity during 500 hours of operation shows that the fabricated panel is reliable during long‐term operation and any abnormal display phenomenon was not observed at 0°C.     

Highly reliable oxide‐semiconductor TFT for AMOLED displays

Abstract— The stability and reliability of oxide‐semiconductor TFTs were investigated. The contact material to the oxide semiconductor affected the thermal stability of the TFT, and a molybdenum‐contact source/drain showed good stability. And the passivating film and TFT structure affected the stability against bias stress and humidity stress, and dc‐sputtered Al²O³ passivation and fully covered channel structure with an etching stopper or source/drain showed good reliability. Moreover, high photo‐stability was confirmed by the bias‐enhanced photo‐irradiation stress test. An 11.7‐in.‐diagonal qHD AMOLED display was demonstrated to provide an applicable solution for a large‐sized OLED and an ultra‐high‐definition LCD‐TV mass production.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.     

Vertically integrated,double stack oxide TFT layers for high‐resolution AMOLED backplane

We developed a novel vertically integrated, double stack oxide thin‐film transistor (TFT) backplane for high‐resolution organic light‐emitting diode (OLED) displays. The first TFT layer is bulk‐accumulation mode, and the second TFT layer is a single gate with back‐channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm²/Vs and 0 ~ 1 V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 μm and a pitch of 18.6 μm was developed, exhibiting well shifted signal up to the last stage of 900 stages without output degradation, which could be used for 1360 ppi TFT backplane.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

Dual‐plate OLED display (DOD) based on amorphous‐silicon (a‐Si) TFT backplane

Abstract— An improved AMOLED with an a‐Si TFT backplane based on a unique structure is reported. The new structure is refered to as a dual‐plate OLED display (DOD). While a top‐emission OLED array is directly fabricated on a TFT backplane, the DOD consists of an upper OLED substrate and a lower TFT substrate, which are independently fabricated. Because the OLED substrate, which is fabricated through the process flow of bottom emission, is attached to the TFT substrate, the light is emitted in the opposite direction to the TFT backplane. The DOD enables the design of large‐sized TFTs and a complicated pixel circuit. It can also not only achieve higher uniformity in luminance in large‐sized displays due to the low electrical resistance of the common electrode, but also wider viewing angles.     

Novel a‐Si:H TFT pixel circuit for electrically stable top‐anode light‐emitting AMOLEDs

Abstract— A novel pixel circuit for electrically stable AMOLEDs with an a‐Si:H TFT backplane and top‐anode organic light‐emitting diode is reported. The proposed pixel circuit is composed of five a‐Si:H TFTs, and it does not require any complicated drive ICs. The OLED current compensation for drive TFT threshold voltage variation has been verified using SPICE simulations.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Power saving through state retention in IGZO‐TFT AMOLED displays for wearable applications

We present a qHD (960 × 540 with three sub‐pixels) top‐emitting active‐matrix organic light‐emitting diode display with a 340‐ppi resolution using a self‐aligned IGZO thin‐film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven‐layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low‐temperature polycrystalline silicon. By using an IGZO thin‐film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low‐refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.     

Development of flexible displays using back‐channel‐etched In–Sn–Zn–O thin‐film transistors and air‐stable inverted organic light‐emitting diodes

We developed flexible displays using back‐channel‐etched In–Sn–Zn–O (ITZO) thin‐film transistors (TFTs) and air‐stable inverted organic light‐emitting diodes (iOLEDs). The TFTs fabricated on a polyimide film exhibited high mobility (32.9 cm²/Vs) and stability by utilization of a solution‐processed organic passivation layer. ITZO was also used as an electron injection layer (EIL) in the iOLEDs instead of conventional air‐sensitive materials. The iOLED with ITZO as an EIL exhibited higher efficiency and a lower driving voltage than that of conventional iOLEDs. Our approach of the simultaneous formation of ITZO film as both of a channel layer in TFTs and of an EIL in iOLEDs offers simple fabrication process.     

New pixel driving circuit using self‐discharging compensation method for high‐resolution OLED micro displays on a silicon backplane

A new 4T2C pixel circuit formed on a silicon substrate is proposed to realize a high‐resolution 7.8‐μm pixel pitch AMOLED microdisplay. In order to achieve high luminance uniformity, the pixel circuit compensates its Vth variation of the MOSFET for the driving transistor internally by using self‐discharging method. Also presented are 0.5‐in Quad‐VGA and 1.25‐in wide Quad‐XGA microdisplays with the proposed pixel circuit.     

Experimental decomposition of the positive bias temperature stress‐induced instability in self‐aligned coplanar InGaZnO thin‐film transistors and its modeling based on the multiple stretched‐exponential functions

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated at several temperatures in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors by combining the stress‐time‐divided measurements and the subgap density‐of‐states (DOS) extraction. It is found that the PBTS‐induced threshold voltage shift (ΔV_T) consists of three mechanisms: (1) increase of DOS due to excess oxygen in the active region; (2) shallow; and (3) deep charge trapping in the gate insulator components. Corresponding activation energy is 0.75, 0.4, and 0.9 eV, respectively. The increase of DOS is physically identified as the electron‐capture by peroxide. Proposed decomposition is validated by reproducing the PBTS time‐evolution of I–V characteristics through the technology computer‐aided design simulation into which the extracted DOS and charge trapping are incorporated. It is also found that the quantitative decomposition of PBTS‐induce ΔV_T accompanied with the multiple stretched‐exponential models enables an effective assessment of the complex degradation nature of multiple PBTS physical processes occurring simultaneously. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for process optimization efforts toward ultimate PBTS stability.