Interface and bulk effects for bias—light‐illumination instability in amorphous‐In—Ga—Zn—O thin‐film transistors

Abstract— Positive‐current‐bias (PB) instability and negative‐bias—light‐illumination (NBL) instability in amorphous‐In—Ga—Zn—O (a‐IGZO) thin‐film transistors (TFTs) have been examined. The channel‐ thickness dependence indicated that the Vth instability caused by the PB stress is primarily attributed to defects in the bulk a‐IGZO region for unannealed TFTs and to those in the channel—gate‐insulator interface for wet‐annealed TFTs. The interface and bulk defect densities (Dit and Nss, respectively) are Dit = 4.8 × 10¹¹ cm^?2/eV and Nss = 7.0×10¹⁶ cm^?3/eV for the unannealed TFT, which increased to 5.2×10¹¹ cm^?2/eV and 9.8×10¹⁶ cm^?3/eV, respectively, by the PB stress test. These are reduced significantly to Dit = 0.82×10¹¹ cm^?2/eV and Nss = 3.2×10¹⁶ cm^?3/eV for the wet‐annealed TFTs and are unchanged by the PB stress test. It was also found that the photo‐response of a‐IGZO TFTs begins at 2.3 eV of photon excitation, which corresponds to subgap states observed by photoemission spectroscopy. The origin of the NBL instability for the wet‐annealed TFTs is attributed to interface effects and considered to be a trap of holes at the channel‐gate—insulator interface where migration of the holes is enhanced by the electric field formed by the negative gate bias.     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

Driver‐circuits‐integrated LCDs based on novel amorphous In‐Ga‐Zn‐oxide TFT

Abstract— A liquid‐crystal panel integrated with a gate driver and a source driver by using amorphous In—Ga—Zn‐oxide TFTs was designed, prototyped, and evaluated. By using the process of bottom‐gate bottom‐contact (BGBC) TFTs, amorphous In—Ga—Zn‐oxide TFTs with superior characteristics were provided. Further, for the first time in the world, a 4‐in. QVGA liquid‐crystal panel integrated with a gate driver and a source driver was developed by using BGBC TFTs formed from an oxide semiconductor. By evaluating the liquid‐crystal panel, its functionality was successfully demonstrate. Based on the findings, it is believed that the novel BGBC amorphous In—Ga—Zn‐oxide TFT will be a promising candidate for future large‐screen backplanes having high definition.     

Amorphous In–Ga–Zn–O thin‐film transistors prepared by magnetron sputtering using Kr and Xe instead of Ar

Heavier noble gases Kr and Xe instead of the lighter Ar during the magnetron‐sputtering deposition of amorphous indium–gallium–zinc oxide films are introduced in fabricating their thin‐film transistors (TFTs). Heavy noble gases can reduce damage to film induced by ion bombardment during the sputtering depositions. Higher field‐effect mobility with better gate bias stability can be obtained in the heavier‐noble‐gas sputtered TFTs. Raman spectroscopic analysis and X‐ray reflectometry respectively suggest that the disordered structure in the film is suppressed, and the film becomes denser by introducing heavy noble gases, corresponding to the improvement of TFT performance.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Effects of gate‐bias stress on ZnO thin‐film transistors

Abstract— The effects of gate‐bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post‐growth annealing conditions using a stretched‐exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier (E^τ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400°C for 30 minutes compared with those annealed for a shorter time.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

A course on thin‐film transistor circuit design for modern displays

A new subject‐specific course on thin‐film transistor (TFT) circuit design is introduced, covering related knowledge of display technologies, TFT device physics, processing, characterization, modeling and circuit design. A design project is required for students to deepen the understanding even more and get hands‐on design experience. This course can be an intense 1‐week course to offer a full training of design engineers in an organized way to meet the ever‐increasing needs in display industry for TFT circuit design specialists. It can also be organized in one semester for electrical engineering Master's and Ph.D. students.     

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Abstract— High‐performance and excellent‐uniformity thin‐film transistors (TFTs) having bottom‐gate structures are fabricated using an amorphous indium‐gallium‐zinc‐oxide (IGZO) film and an amorphous‐silicon dioxide film as the channel layer and the gate insulator layer, respectively. All of the 94 TFTs fabricated with an area 1 cm² show almost identical transfer characteristics: the average saturation mobility is 14.6 cm²/(V‐sec) with a small standard deviation of 0.11 cm²/(V‐sec). A five‐stage ring‐oscillator composed of these TFTs operates at 410 kHz at an input voltage of 18 V. Pixel‐driving circuits based on these TFTs are also fabricated with organic light‐emitting diodes (OLED) which are monolithically integrated on the same substrate. It is demonstrated that light emission from the OLED cells can be switched and modulated by a 120‐Hz ac signal input. Amorphous‐IGZO‐based TFTs are prominent candidates for building blocks of large‐area OLED‐display electronics.     

a‐InGaZnO thin‐film transistors for AMOLEDs: Electrical stability and pixel‐circuit simulation

Abstract— Inverted‐staggered amorphous In‐Ga‐Zn‐O (a‐InGaZnO) thin‐film transistors (TFTs) were fabricated and characterized on glass substrates. The a‐InGaZnO TFTs exhibit adequate field‐effect mobilities, sharp subthreshold slopes, and very low off‐currents. The current temperature stress (CTS) on the a‐InGaZnO TFTs was performed, and the effect of stress temperature (TSTR), stress current (ISTR), and TFT biasing condition on their electrical stability was investigated. Finally, SPICE modelling for a‐InGaZnO TFTs was developed based on experimental data. Several active‐matrix organic light‐emitting‐display (AMOLED) pixel circuits were simulated, and the potential advantages of using a‐InGaZnO TFTs were discussed.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The V_T variation increases sharply as the channel length decreases because of the large resistance R_offset when it is formed at a‐IGZO source/drain. In the experiment, R_offset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.     

Instability dependent upon bias and temperature stress in amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors

Abstract— The effects of gate‐bias stress, drain‐bias stress, and temperature on the electrical parameters of amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors have been investigated. Results demonstrate that the devices suffer from threshold‐voltage instabilities that are recovered at room temperature without any treatments. It is suggested that these instabilities result from the bias field and temperature‐assisted charging and discharging phenomenon of preexisting traps at the near‐interface and the a‐IGZO channel region. The experimental results show that applying a drain‐bias stress obviously impacts the instability of a‐IGZO TFTs; however, the instability caused by drain bias is not caused by hot‐electron generation as in conventional MOSFETs. And the degradation trend is affected by thermally activated carriers at high temperature.     

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors with wet‐etched electrodes

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors (a‐IGZO TFTs) with wet‐etched electrodes was employed in this paper. Five metals (Al, Cu, Ti, Ta, and Cr) as well as various etchants were comparatively investigated, indicating H₂O₂ based solution etched Ta films were good candidates for the wet‐etched electrodes of a‐IGZO TFTs. The aforementioned findings along with other improving attempts successfully established inexpensive processing steps and conditions with which stable a‐IGZO TFTs were finally fabricated. The device performance was reasonably good enough (μ_FE of 6.0 cm²/V·s, V_th of 2.5 V, SS of 1.8 V/decade, and I_on/I_off of 10⁶) to meet the requirements of applications especially for small‐sized flat panel displays.     

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

An indium–gallium–zinc oxide or a zinc–tin oxide thin‐film transistor (TFT) fabricated when the relative humidity in the laboratory is less than 50% is found to exhibit good electrical performance, with an abrupt, distortion‐free transfer curve and a turn‐on voltage close to 0 V. In contrast, when such an amorphous oxide semiconductor (AOS) TFT is fabricated at a relative humidity greater than 50%, its “as‐fabricated” electrical performance is very poor, typically characterized by a large amount of hysteresis, a strongly negative turn‐on voltage, and a kink‐like distortion in the subthreshold region of its transfer curve. However, the electrical performance of such a poor‐quality TFT is observed to improve over time, if it is simply stored in the dark at room temperature without being subjected to electrical stress. This recovery usually requires weeks (months) for an unpassivated (passivated) AOS TFT. Recovery is tentatively ascribed to the gradual removal of moisture from the AOS TFT channel layer.     

Comparative study on extraction methods of threshold voltage for thin‐film transistors

In this work, we proposed three methods on extracting threshold voltage of ploy‐silicon thin‐film transistors, such as, extrapolation of the linear region, transconductance linear extrapolation, and second derivation. Based on these different methods, one can extract various values of threshold voltages, as well as their temperature dependence. In room temperature, the second derivation method is the most appropriate for thin‐film transistors. More remarkably, the different methods show the different temperature dependence of mobility, corresponding to different charge transport mechanisms. That is, hopping dominates the transport mechanism for extrapolation of the linear region method, while it will occur to transform from band‐like to hopping mechanism for the second derivative method.     

Development of flexible displays using back‐channel‐etched In–Sn–Zn–O thin‐film transistors and air‐stable inverted organic light‐emitting diodes

We developed flexible displays using back‐channel‐etched In–Sn–Zn–O (ITZO) thin‐film transistors (TFTs) and air‐stable inverted organic light‐emitting diodes (iOLEDs). The TFTs fabricated on a polyimide film exhibited high mobility (32.9 cm²/Vs) and stability by utilization of a solution‐processed organic passivation layer. ITZO was also used as an electron injection layer (EIL) in the iOLEDs instead of conventional air‐sensitive materials. The iOLED with ITZO as an EIL exhibited higher efficiency and a lower driving voltage than that of conventional iOLEDs. Our approach of the simultaneous formation of ITZO film as both of a channel layer in TFTs and of an EIL in iOLEDs offers simple fabrication process.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.