Signal‐noise support vector model of a microwave transistor

In this work, a support vector machines (SVM) model for the small‐signal and noise behaviors of a microwave transistor is presented and compared with its artificial neural network (ANN) model. Convex optimization and generalization properties of SVM are applied to the black‐box modeling of a microwave transistor. It has been shown that SVM has a high potential of accurate and efficient device modeling. This is verified by giving a worked example as compared with ANN which is another commonly used modeling technique. It can be concluded that hereafter SVM modeling is a strongly competitive approach against ANN modeling. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Temperature‐dependent models of low‐noise microwave transistors based on neural networks

Neural networks are proposed for efficient temperature‐dependent modeling of small‐signal and noise performances of low‐noise microwave transistors over a wide temperature range. The proposed models can be based either on neural networks only or on a combination of neural networks and empirical transistor models. © 2005 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2005.     

Modeling power and intermodulation behavior of microwave transistors with unified small‐signal/large‐signal neural network models

This article presents a detailed procedure to learn a nonlinear model and its derivatives to as many orders as desired with multilayer perceptron (MLP) neural networks. A modular neural network modeling a nonlinear function and its derivatives is introduced. The method has been used for the extraction of the large‐signal model of a power MESFET device, modeling the nonlinear relationship of drain‐source current I_ds as well as gate and drain charge Q_g and Q_d with respect to intrinsic voltages V_gs and V_ds over the whole operational bias region. The neural models have been implemented into a user‐defined nonlinear model of a commercial microwave simulator to predict output power performance as well as intermodulation distortion. The accuracy of the device model is verified by harmonic load‐pull measurements. This neural network approach has demonstrated to predict nonlinear behavior with enough accuracy even if based only on first‐order derivative information. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13: 276–284, 2003.     

Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

Bayesian inference‐based small‐signal modeling technique for GaN HEMTs

A new modeling methodology for gallium nitride (GaN) high‐electron‐mobility transistors (HEMTs) based on Bayesian inference theory, a core method of machine learning, is presented in this article. Gaussian distribution kernel functions are utilized for the Bayesian‐based modeling technique. A new small‐signal model of a GaN HEMT device is proposed based on combining a machine learning technique with a conventional equivalent circuit model topology. This new modeling approach takes advantage of machine learning methods while retaining the physical interpretation inherent in the equivalent circuit topology. The new small‐signal model is tested and validated in this article, and excellent agreement is obtained between the extracted model and the experimental data in the form of dc I–V curves and S‐parameters. This verification is carried out on an 8 × 125 μm GaN HEMT with a 0.25 μm gate feature size, over a wide range of operating conditions. The dc I–V curves from an artificial neural network (ANN) model are also provided and compared with the proposed new model, with the latter displaying a more accurate prediction benefiting, in particular, from the absence of overfitting that may be observed in the ANN‐derived I–V curves.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Complete parasitic‐capacitance‐shell extraction of high‐frequency switch‐HEMT equivalent‐circuit model

This paper presents a new solution to a particular problem of high electron‐mobility transistor (HEMT) equivalent‐circuit modeling, that is, complete parasitic‐capacitance‐shell extraction of high‐frequency single‐gate and dual‐gate switch‐based HEMTs, which is very important to the accuracy of high‐frequency HEMT switch models, but not important in the conventional common‐source HEMT modeling for amplifier‐applications. A full‐wave electromagnetic (EM) analysis based method is proposed to analytically extract the complete parasitic‐capacitance‐shell of single‐gate and dual‐gate switch‐based HEMTs. All the 6 parasitic capacitances of the single‐gate switch‐based HEMT and all the 10 parasitic capacitances of the dual‐gate switch‐based HEMT are extracted by linear equations. No resistance parameter is needed to calculate the capacitance‐to‐ground and the interelectrode‐capacitance, and for the first time, all the 10 parasitic capacitances of the dual‐gate switch‐based HEMT are completely considered and analytically extracted. Then, a consistent and systematic modeling procedure of single‐gate and dual‐gate switch‐based HEMT is verified. With the complete parasitic‐capacitance‐shells extracted, the accurate intrinsic model of the single‐gate HEMT can be directly embedded into the parasitic‐shell of the dual‐gate HEMT. The predicted scattering parameters of the single‐gate and dual‐gate series switches fit well with the measurements up to 40 GHz, and accurate linear scalability are also found.     

Design of a 10 W high‐efficiency balanced power amplifier using a combination of load‐pull and load‐line methods for ISM band

In this article, a 10 W power amplifier has been designed and constructed at 2.4 GHz. The source and load‐pull impedance data published by the manufacturer at a nearby frequency of 2.5 GHz have been adopted to power match the transistor at the intended design frequency. For this purpose, the linear model of the GaN transistor has been derived from the S‐parameter data. The load‐line at the dependent current source plane and the impedance at the intrinsic gate‐source capacitance have been simulated in the presence of the source and load‐pull impedances at 2.5 GHz. The extracted impedances have been retained in the design of the power amplifier at 2.4 GHz. In a novel approach, the input and output matching circuits interacted with the linear model of the transistor to provide the same load‐line conditions at the virtual drain plane and the intrinsic gate‐source capacitance plane. In contrast to conventional load‐pull methods that give no information about the harmonic terminations, harmonic terminations can be easily controlled in this method. The insight into the transistor linear model allows the harmonic terminations at the virtual drain plane to be set to low values for proper class‐B operation.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

The study of oxide‐interface and grain‐boundary traps in poly‐Si TFT characteristics and its application to fabrication process diagnosis

Abstract— The study of oxide‐interface and grain‐boundary traps in poly‐Si TFT characteristics is reviewed. The subthreshold swing and threshold voltage mainly depend on the density of the oxide‐interface traps (Dit), while the transistor mobility mainly depends on the density of grain‐boundary traps (Dgb). These device properties are applied to diagnose two fabrication processes: plasma treatment and gate‐oxide deposition. It is found that oxygen (O) plasma treatment reduces Dit. This seems to be because O plasma treatment has the ability to terminate the dangling bonds, but O plasma species do not diffuse into the poly‐Si. A model is proposed by comparing the bond energy of the Si‐H and Si‐O‐H. On the other hand, plasma‐enhanced chemical‐vapor deposition (PECVD) of tetraethylorthosilicate (TEOS) for gate oxide increases Dgb. This seems to be because hydrogen (H) plasma species in the TEOS‐PECVD damage the grain boundaries. A model is proposed by considering the reaction processes: hydrolysis, dehydration and bonding, and H plasma species generated during the dehydration.     

Microwave noise modeling for PHEMT using artificial neural network technique

An improved noise model for pseudomorphic high electron mobility transistors (PHEMT) based on the combination of the artificial neural network (ANN) and conventional equivalent circuit modeling technique is presented. The frequency dispersion of the gate noise model parameter P, drain noise model parameter R, and the correlation coefficient C have been taken into account by using an ANN model. The influence of the gate leakage current can be accommodated by using the proposed noise model. The noise model parameters are determined directly from on wafer noise parameters measurement based on the noise correlation matrix technique. Good prediction for noise parameters and significant improvements of the accuracy of noise parameters are obtained up to 26 GHz for 2 × 40 μm gate width (number of gate fingers × unit gate width) 0.25 μm Double Heterojunction δ‐doped PHEMTs over a wide range of bias points. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Scale‐invariant segmentation of dynamic contrast‐enhanced perfusion MR images with inherent scale selection

Selection of the best set of scales is problematic when developing signal‐driven approaches for pixel‐based image segmentation. Often, different possibly conflicting criteria need to be fulfilled in order to obtain the best trade‐off between uncertainty (variance) and location accuracy. The optimal set of scales depends on several factors: the noise level present in the image material, the prior distribution of the different types of segments, the class‐conditional distributions associated with each type of segment as well as the actual size of the (connected) segments. We analyse, theoretically and through experiments, the possibility of using the overall and class‐conditional error rates as criteria for selecting the optimal sampling of the linear and morphological scale spaces. It is shown that the overall error rate is optimized by taking the prior class distribution in the image material into account. However, a uniform (ignorant) prior distribution ensures constant class‐conditional error rates. Consequently, we advocate for a uniform prior class distribution when an uncommitted, scale‐invariant segmentation approach is desired. Experiments with a neural net classifier developed for segmentation of dynamic magnetic resonance (MR) images, acquired with a paramagnetic tracer, support the theoretical results. Furthermore, the experiments show that the addition of spatial features to the classifier, extracted from the linear or morphological scale spaces, improves the segmentation result compared to a signal‐driven approach based solely on the dynamic MR signal. The segmentation results obtained from the two types of features are compared using two novel quality measures that characterize spatial properties of labelled images. Copyright © 2002 John Wiley & Sons, Ltd.     

The new route for realization of 1‐μm‐pixel‐pitch high‐resolution displays

A new pixel structure for the realization of a 1‐μm‐pixel‐pitch display was developed. This structure, named vertically stacked thin‐film transistor (VST), was based on the conventional back‐channel etched thin‐film transistor (TFT), but all the layers except the horizontal gate line were vertically stacked on the embedded data line, enabling the implementation of high‐resolution display panels. The VST device with a channel length of 1 μm showed a high field effect mobility of more than 50 cm²/Vs and low subthreshold slope of 78 mV per decade. It also shows a high uniform electrical characteristic over the entire 6‐in. wafer. The development of a new pixel architecture is expected to enable the implementation of 1‐μm‐pixel‐pitch high‐resolution displays such as spatial light modulators for digital holograms.     

Application of data mining methods to efficient microwave active device modeling

In this work, the signal and noise behaviors of a microwave transistor within its operation domain (voltage drain to source–V_DS, current of drain to source—I_DS, frequency—f) are modeled by data mining techniques (DMT) without using any information on the microwave circuit theory. The device is modeled by a black box whose small signal (S) and noise parameters are evaluated through data mining techniques, based on the fitting of both of these parameters for multiple bias and configuration. It has been shown that DMT have a high potential of faithful and efficient device modeling. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

Design and analysis of a WLAN CMOS power amplifier using multiple‐gated transistor technique

This article focused on 5.2 GHz highly integrated power amplifier for IEEE 802.11a WLAN application. Multiple‐gated transistor technique was used to improve linearity. A new approach for choosing the bias voltage of auxiliary transistor by analyzing the shift of gate bias is used in the design. The simulated results of the proposed two‐stage differential power amplifier indicate 25.28 dBm P_1‐dB, 32.87% PAE, and 26.18 dBm saturated output power with a 5.2 dB P_1‐dB improvement compared to conventional single transistor amplifier. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

Genetic algorithm‐based neural‐network modeling approach applied to AlGaN/GaN devices

An accurate equivalent circuit large‐signal model (ECLSM) for AlGaN‐GaN high electron mobility transistor (HEMT) is presented. The model is derived from a distributed small‐signal model that efficiently describes the physics of the device. A genetic neural‐network‐based model for the gate and drain currents and charges is presented along with its parameters extraction procedure. This model is embedded in the ECLSM, which is then implemented in CAD software and validated by pulsed and continuous large‐signal measurements of on‐wafer 8 × 125‐μm GaN on SiC substrate HEMT. Pulsed IV simulations show that the model can efficiently describe the bias dependency of trapping and self‐heating effects. Single‐ and two‐tone simulation results show that the model can accurately predict the output power and its harmonics and the associated intermodulation distortion (IMD) under different input‐power and bias conditions. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

Microwave frequency small‐signal equivalent circuit parameter extraction for AlInN/GaN MOSHEMT

This article presents an accurate and efficient extraction procedure for microwave frequency small‐signal equivalent circuit parameters of AlInN/GaN metal‐oxide‐semiconductor high electron mobility transistor (MOSHEMT). The parameter extraction technique is based on the combination of conventional and optimization methods using the computer‐aided modeling approach. The S‐, Y‐, and Z‐ parameters of the model are extracted from extensive dynamic AC simulation of the proposed device. From the extracted Y‐ and Z‐ parameters the pad capacitances, parasitic inductances and resistances are extracted by operating the device at low and high frequency pinch‐off condition depending upon requirement. Then, the intrinsic elements are extracted quasi analytically by de‐embedding the extrinsic parameters. S‐parameter simulation of the developed small‐signal equivalent circuit model is carried out and is compared with TCAD device simulation results to validate the model. The gradient based optimization approach is used to optimize the small‐signal parameters to minimize the error between developed SSEC model and device simulation based s‐parameters. The microwave characteristics of optimized SSEC model is carried out (f_T = 169 GHz and f_max = 182 GHz) and compared with experimental data available from literature to validate the model.     

Amorphous‐oxide TFT backplane for large‐sized AMOLED TVs

Abstract— Amorphous‐oxide thin‐film‐transistor (TFT) arrays have been developed as TFT backplanes for large‐sized active‐matrix organic light‐emitting‐diode (AMOLED) displays. An amorphous‐IGZO (indium gallium zinc oxide) bottom‐gate TFT with an etch‐stop layer (ESL) delivered excel lent electrical performance with a field‐effect mobility of 21 cm²/V‐sec, an on/off ratio of >10⁸, and a subthreshold slope (SS) of 0.29 V/dec. Also, a new pixel circuit for AMOLED displays based on amorphous‐oxide semiconductor TFTs is proposed. The circuit consists of four switching TFTs and one driving TFT. The circuit simulation results showed that the new pixel circuit has better performance than conventional threshold‐voltage (VTH) compensation pixel circuits, especially in the negative state. A full‐color 19‐in. AMOLED display with the new pixel circuit was fabricated, and the pixel circuit operation was verified in a 19‐in. AMOLED display. The AMOLED display with a‐IGZO TFT array is promising for large‐sized TV because a‐IGZO TFTs can provide a large‐sized backplane with excellent uniformity and device reliability.     

Static active‐matrix OLED display without pixel refresh enabled by amorphous‐silicon non‐volatile memory

Abstract— An active‐matrix organic light‐emitting‐diode (AMOLED) display which does not require pixel refresh is demonstrated. This was achieved by replacing the thin‐film transistor (TFT) that drives the OLED with a non‐volatile memory TFT, in a 2‐transistor pixel circuit. The threshold voltage of the non‐volatile‐memory TFT can be changed by applying programming voltage pulses to the gate electrode. This approach eliminates the need for storage capacitors, increases the pixel fill factor, and potentially reduces power consumption. Each pixel can be individually programmed or erased using a standard active‐matrix addressing scheme. The programmed image is stored in the display even if power is turned off.     

On‐Site Example‐Based Material Appearance Acquisition

We present a novel example‐based material appearance modeling method suitable for rapid digital content creation. Our method only requires a single HDR photograph of a homogeneous isotropic dielectric exemplar object under known natural illumination. While conventional methods for appearance modeling require prior knowledge on the object shape, our method does not, nor does it recover the shape explicitly, greatly simplifying on‐site appearance acquisition to a lightweight photography process suited for non‐expert users. As our central contribution, we propose a shape‐agnostic BRDF estimation procedure based on binary RGB profile matching. We also model the appearance of materials exhibiting a regular or stationary texture‐like appearance, by synthesizing appropriate mesostructure from the same input HDR photograph and a mesostructure exemplar with (roughly) similar features. We believe our lightweight method for on‐site shape‐agnostic appearance acquisition presents a suitable alternative for a variety of applications that require plausible “rapid‐appearance‐modeling”.