Use of self‐erase discharges for high‐speed and low‐voltage addressing of PDPs

Abstract— A technique called “self‐erase‐discharge addressing” has been incorporated with a address‐while‐display driving scheme, contiguous subfield, and erase addressing to obtain high‐speed and low‐voltage addressing of PDPs. The technique uses a relatively high X‐sustain pulse voltage VXsus, which produces a weak self‐erase discharge at its trailing edge. An application of a data pulse Vdata synchronous to a weak self‐erase discharge results in full erase discharge and eliminates all the wall charges. The technique assures a wider operating‐voltage margin since it provides identical amounts of priming charges as well as wall charges to all the horizontal scan lines just prior to addressing. The priming charges are generated by the weak self‐erase discharges, resulting in low Vdata of 30 V and a high addressing speed of 0.66 μsec for a Ne + 10% Xe PDP. V_Xsus = 245 V, and the voltage margins of Vdata and VXsus were 35 and 16 V, respectively. For a 30% Xe PDP, Vdata and VXsus were 30 and 335 V, respectively, with an addressing speed of 1.0 μsec. In order to obtain high dark‐room contrast, it is essential to use ramp reset pulses, with which erase addressing cannot be achieved. By adopting the write addressing only to the first subfield and the self‐erase‐discharge addressing to the subsequent subfields, a peak and background luminance in green of 3100 and 0.22 cd/m², respectively, were obtained with a dark‐room contrast of 14,000:1. The number of subfields was 28, and the light emission duty was 83%. The number of ramp reset pulse drivers could be reduced to 12 by adopting the common reset pulse technique.     

Feasibility of driving PDPs with 1‐V data and 30‐V scan pulses by controlling the self‐erase‐discharge threshold

Abstract— In order to realize low‐voltage addressing of PDPs, an erase‐addressing scheme was adopted together with an accumulation of an appropriate amount of wall charge by using priming and bias pulses prior to addressing. The switching operation is performed by using sharp threshold characteristics of the self‐erase discharge. Cessation of the scan pulse ignites a weak self‐erase discharge, which, together with the data pulse, triggers an intense self‐erase discharge. By using the drive scheme, the data‐ and scan‐pulse voltages can be reduced to 1.1 and 29.6 V, respectively, provided that the panel has perfectly uniform voltage characteristics.     

High‐speed low‐voltage driving of high‐Xe‐content PDPs with priming particles

Abstract— Power savings, image‐quality improvement, and cost reduction are the major issues facing PDP development. High‐Xe‐content PDPs have attained improved luminous efficiency, but with sacrifices in higher switching and sustain voltages and slower discharge build‐up. By examining PDPs having 3.5%–30% Xe content, it was found that utilization of the space‐charge priming effect as well as wall‐charge accumulation are effective in obtaining a low operating voltage and a high switching speed. The improvements are enhanced for higher Xe pressures. By using space‐charge priming, the statistical time lag of the discharge triggering for the 30% Xe content is reduced significantly and becomes approximately equal to that of 3.5% Xe content. Once triggered, the formative time lag of the discharge becomes shorter and the space charge experiences diffusion/drift; hence, accumulation of the wall charge is faster for discharges with higher Xe contents. These indicate that the use of an erase addressing scheme, rather than a write addressing scheme, is preferable when driving high Xe‐content PDPs, because the erase addressing scheme provides the addressing operation with an abundant amount of priming particles. Also, the drive voltages are lower for the erase addressing scheme. In order to reduce the address voltage, it is effective to accumulate wall charges prior to addressing. It was found that there are limiting values for the charge accumulation, above which self‐erase discharges ignite and the wall charge is dissipated. The self‐erase discharge occurs at relatively low wall voltages when the Xe percentages becomes higher. The sustain pulse voltage can be reduced while keeping the luminous efficiency high by increasing the sustain pulse frequency. As the frequency is increased, a residual amount of space charge created by the preceding sustain pulse increases. Due to the priming effect of these space charge, the build‐up of the discharge current becomes faster, resulting in a lower voltage.     

Discharge characteristics and low‐voltage driving of high‐Xe‐content PDPs

Abstract— High‐Xe‐content PDPs attain improved luminous efficiency, but with sacrifices of higher sustain and address voltages and slower discharge build‐up. By examining PDPs with 3.5–100% Xe contents, it was revealed that space‐charge priming as well as wall‐charge accumulation are effective in obtaining low‐voltage and high‐speed operation. In addition, it was found that the effectiveness is emphasized for higher‐Xe‐pressure PDPs. In this respect, erase addressing is more favorable than write addressing, especially for high‐Xe‐pressure PDPs. The formative time lag of the discharge and diffusion/drift of the space charges are shorter for high Xe contents. In this respect, high‐Xe‐content PDPs have a potential for high‐speed addressing, if driven adequately. The use of space‐charge priming, however, is limited by the duration between the priming and scan pulses. Accumulation of wall charges is limited by ignition of a self‐erase discharge with which all the wall charges are dissipated. Although the highest efficiency and luminance are attained with a 100%‐Xe panel, the optimum Xe gas content, considering the sustain pulse voltage and drive voltage margin, would be 70% Xe + Ne.     

Data‐pulse‐voltage reduction of AC‐PDPs by using metastable‐particle priming

Abstract— It is shown that space charges dominate the build‐up of an address discharge when it is preceded by a priming discharge in less than 32 μsec. When the separation of these discharges (cease period) exceeds 32 μsec, the space charges diffuse away and the metastable particles start playing the role of priming. The priming effect of the metastable particles is not too strong, which is desirable for adopting a data‐pulse‐voltage reduction technique for PDPs. By choosing the length of the cease period to be between 32 and 80 μsec in the Address‐While‐Display drive scheme, the data pulse voltage was reduced to 20 V. This leads to a considerable cost reduction of data driver ICs.     

Address‐While‐Display technique combined with gas‐discharge AND logic for driving AC‐PDPs

A hybrid AWD/AND drive technique has been developed in which an Address‐While‐Display (AWD) scheme is combined with an AND logic characteristic that gas discharges demonstrate. The AWD technique enables AC‐PDPs to be driven at high luminance, while the AND logic reduces the number of scan drivers by an order of magnitude. A detailed analysis of the addressing operation has been made. The hybrid drive utilizes the AND logic in two ways: (1) a combination of two voltage pulses and (2) a combination of a voltage pulse and discharge‐priming particles. It was found that the addressing operation requires the establishment of a discharge between the scan and data electrodes, and also between the scan and display electrodes.     

Improved discharge time lag of address pulse in an ACPDP with auxiliary electrodes

Abstract— New driving waveforms are proposed for an ACPDP with an auxiliary electrode. Auxiliary pulses and a stepped scan pulse during the address period distinguish the proposed waveforms from conventional waveforms. The address discharge time lag in an ACPDP with auxiliary electrodes was improved by application of auxiliary pulses and a stepped scan pulse during the address period. The interaction between the auxiliary pulse and the stepped scan pulse generates priming particles directly prior to the address discharge, and these priming particles influence the address discharge. As a result, the firing voltage of the address pulse is lowered, and the minimum address voltage is lower than that of conventional driving waveforms. Experimental results confirm that the address discharge time lag of the proposed waveforms is 32% lower than that of conventional driving waveforms.     

High‐frequency drive of high‐Xe‐content PDPs for high efficiency and low‐voltage performance

Abstract— It has been well known that the luminous efficiency of PDPs can be improved by increasing the Xe content in the panel. For instance, the efficiency is improved by a factor 1.7 when the Xe content is increased from 3.5% to 30%. The sustain pulse voltage, however, increases from 180 to 230 V by a factor 1.3. It was found that the increase in the sustain pulse voltage can be suppressed by increasing the sustain pulse frequency. The high‐frequency operation further increases the luminous efficiency. If the Xe content is increased from 3.5% to 30% and the drive pulse frequency is increased from 147 to 313 kHz, the luminous efficiency becomes 2.7 times higher and the luminance 4.5 times higher. Furthermore, the increase in the sustain pulse voltage is suppressed 1.1 times, from 180 to 200 V. A mechanism of attaining high efficiency and low‐voltage performance can be considered as follows. A train of pulses is applied during a sustain period. As the sustain pulse frequency is increased, the pulse repetition rate becomes faster and a percentage of the space charge created by the previous pulse remains until the following pulse is applied. Due to the priming effect of these space charge, the discharge current build‐up becomes faster, the width of the discharge current becomes narrower, ion‐heating loss is reduced, and the effective electron temperature is optimized so that Xe atoms are excited more efficiently. The intensity of Xe 147‐nm radiation, dominant in low‐pressure Xe dis‐charges, saturates with respect to electron density due to plasma saturation. This determines the high end of the sustain pulse frequency.     

Analysis of the driving characteristics for an ACPDP with an auxiliary electrode using the voltage‐transfer closed surface

Abstract— The driving characteristics and wall‐charge model of an ac plasma‐display panel (ACPDP) with an auxiliary electrode were investigated by using voltage‐transfer closed‐surface modeling. To understand the wall‐charge behavior of an ACPDP with an auxiliary electrode qualitatively, voltage‐transfer closed‐surface analysis was applied to a test panel under the full driving waveform. The voltage‐transfer closed surfaces were obtained after the sustain, reset, and address periods, when the full‐stage driving waveform was employed with the test panel. As a result, it was proven that the wall‐charge model predicted in the previous work corresponded with the wall‐charge behavior of an ACPDP with an auxiliary electrode. Also, based on the resultant form after the address period, the wall‐charge model after the address period was recently added and the entire wall‐charge model was completed in this work. In addition, by investigating the trajectory of the cell‐state movement during the reset period, it was confirmed that the priming effect affected the reduced discharge time lag of an ACPDP with an auxiliary electrode under the newly proposed driving waveform for reducing address time lag.     

High‐efficacy drive of spatial positive‐column‐discharge PDP with delayed D pulses

Abstract— A thick‐film ceramic‐sheet PDP provides a long sustain discharge gap of 0.45 mm, enabling the use of positive column discharges. The discharges are established in the middle of the discharge space and are completely free from touching the surface of substrates. This allows for the reduction in diffusion losses of the charged particles. To further improve the efficacy, delayed D pulses are applied to the address electrodes during the sustain period. Although the pulses only draw a little current, they perturb the electric field, reducing the peak discharge current and hence resulting in higher efficacy and luminance. The efficacy and luminance increase by 35% and 38%, respectively, with the delayed D pulses. These pulses are incorporated into the contiguous‐subfield erase‐addressing drive scheme for TV application. A short gap of 70 μm between the sustain and data electrodes generates a fast‐rising discharge and allows a high‐speed addressing of 0.25 μsec. This provides 18 contiguous subfields for the full‐HD single‐scan mode, with 70% light emission duty. A luminous efficacy of 6.0 lm/W can been attained using Ne + 30% Xe 47 kPa, a sustain voltage of 320 V, and a sustain frequency of 3.3 kHz, when the luminance is 157 cd/m². Alternatively, the panel can achieve 4.2 lm/W and 1260 cd/m² by increasing the sustain frequency to 33 kHz.     

High‐contrast driving method for advanced CEL structure with magnesium oxide single‐crystal powder in ACPDP

Abstract— A new driving method for an advanced‐CEL‐structure panel has been developed. Picture qualities have been upgraded. Discharge time lags are drastically shortened by priming electron emission from magnesium oxide (MgO) single‐crystal powder, refered to as a crystal emissive layer (CEL). The advanced‐CEL‐structure panel has CEL material on the surface of not only the surface‐discharge‐electrode side but also on the address‐electrode side. This panel structure enables a stable opposed discharge when the address electrode functions as a cathode. By utilizing the opposed discharges in the reset and LSB‐SF sustain periods, the dark‐room contrast ratio has been drastically increased to over 20,000:1, which is higher than five times that of the conventional method, and the luminance of the least‐significant‐bit sub‐field (LSB‐SF) is as low as 0.1 cd/m², which is one‐fourth that of the conventional method. The high‐picture‐quality PDP TVs refered to as “KURO” that employs these technologies have been introduced into the marketplace.     

Effects of Xe content on wall‐voltage variation during address period in AC plasma‐display panel

Abstract— To investigate the influence of the gas condition, especially xenon (Xe) gas, on the wall‐voltage variation in relation to the electric‐field intensity during the address period, the wall voltages were measured under various Xe‐gas content ranging from 11 to 20% by using the V^t closed curve analysis method. It was observed that under a weak electric‐field intensity between the scan and address electrodes, the change in Xe content did not affect the wall‐voltage variation, even at a higher panel temperature of 65δC. However, under a strong electric‐field intensity, the wall‐voltage variations were reduced with an increase in the Xe content, confirming that a higher electric‐field intensity would be required to induce the wall‐voltage variation at a higher Xe content during the address period.     

Performance of the efficacy enhancement layer using nano‐particles in PDPs

Abstract— A nano‐particle dielectric layer was experimentally placed between a conventional dielectric layer and a MgO thin film. This greatly reduces the discharge current and enhances high luminous efficacy. The current reduction might reflect a capacitance reduction in the entire dielectric layer due to the extremely low permittivity of the nano‐particle layer which includes a large amount of space. The luminous efficacy is improved more than what is expected because of the reduction in capacitance. The layer affects the MgO film properties such as crystal growth size, orientation, cathode luminescence, and exo‐electron emission. As a result, it improves the statistical delay in addressing. This might be caused by the large crystal growth of MgO due to the surface roughness of the nano‐particle layer underneath. The particle size required to optimize the roughness of the large growth is about 10–50 nm. The rise in the discharge voltage accompanied by the nano‐particle layer insertion is improved when the layer is properly patterned. A reduction in luminance is prevented when it is patterned in narrow lines along the X—Y gaps while the improvement in address delay strongly depends on the areal ratio of the nano‐particle layer.     

The 121‐contiguous‐subfield addressing of high Xe‐content PDPs

Abstract— As the Xe content of PDPs is increased, the space‐charge priming becomes more effective. Also, the diffusion/drift of the space charges and accumulation of the wall charges becomes faster. These facts indicate that the use of an erase addressing is preferable for high‐Xe‐content PDPs. A 30%‐Xe green test panel was driven with contiguous subfields using erase addressing and a grouped Address‐While‐Display scheme. Crosstalk was suppressed by driving the odd and even sustain electrodes separately. The fast addressing speed of 0.283 μsec allowed for 121 subfields and 122 gray levels, with a resultant luminance of 4200 cd/m² and a dark‐room contrast of 310:1. The scan and data pulse voltages were as low as 90 and 75 V, respectively. All the subfields had an identical length of 136 μsec, but the number of sustain pulses in these subfields could be varied between 2 and 20. By selecting an adequate number of sustain pulses in the subfields, arbitrary gamma characteristics could be realized. A gray‐scale expression having a constant difference between the consecutive “perceived” luminance levels was verified throughout all the luminance levels.     

High‐speed driving waveform based on reset and address discharge analysis using a Vt closed curve in ACPDPs

Abstract— Driving waveforms having both high‐speed address and low background were developed using V_t closed curve analysis. To prevent a misfired discharge during a sustain period, the voltage difference at the end of the ramp setup between the X‐Y electrodes remains constant. Because background luminance becomes higher (although the address discharge time lag becomes shorter) as the voltage difference between the A‐Y electrodes becomes larger, a low reset voltage and an address bias voltage were adopted during the ramp‐up period.     

Effects of shadow‐mask voltage on the discharge in shadow‐mask PDPs

Abstract— A new type of ACPDP with a shadow mask (shadow‐mask PDP, SMPDP) has been developed, featuring an effective structure and lower cost. The distinct difference between an SMPDP and a conventional ACPDP is that the dielectric barrier ribs are replaced by a single metal shadow mask. A three‐dimensional self‐consistent fluid model was used to analyze the effects of the shadow‐mask voltage on the discharge for a simplified driving scheme. The simulation results indicate that by selecting the appropriate shadow‐mask voltage, the addressing speed can be improved due to the local strong electric field. The steady discharge in the sustaining period will not be affected by changes in the shadow‐mask voltages in the addressing period. While in the sustaining period, the shadow‐mask‐voltage variation can directly affect the sustaining discharge. The floating shadow mask in the sustaining period is beneficial in achieving a stable sustaining discharge.     

Effect of single crystalline MgO powder treatment of phosphor surface on discharge property of high-Xe AC plasma display panels

This paper presents a method of surface treatment of phosphor using a single crystalline MgO powder, and investigates effect of the surface treatment on discharge property of a plasma display panel (PDP). The discharge gas of the PDP was a 88% Ne–12% Xe gas mixture at a pressure of 400 Torr. For the surface treatment, a single crystalline MgO powder was mixed in methanol, sprayed on the phosphor surface, and annealed at 400 °C. This treatment suppressed glow discharge, which was observed very often in the weak discharges for reset of PDP if the phosphor works as a cathode, and provided a favorable condition for the PDP reset operation. When an experimental PDP fabricated using the surface treatment was driven by the twin reset waveform, the measured time delay for 99.9% cumulative probability of address discharge was 830 ns, which meets the timing requirement for addressing a Full HD (1920 × 1080 resolution) PDP with the 10 sub-field single scan method.     

High‐efficiency PDP micro‐discharges

Abstract— High‐efficiency plasma‐display‐panel micro‐discharge characteristics will be discussed. An increase in the discharge efficiency for a higher‐Xe‐content gas mixture is well known. In this article, the interdependency of the capacitive design, the sustain voltage, and the Xe content will be discussed. A high panel efficacy was obtained, especially for the design and driving conditions that govern the development of a fast discharge. A fast discharge was observed for a higher discharge field at sustain voltages higher than 200 V. A +C‐buffer design, where the extra capacitance acts as a local on the panel power source that lowers the voltage decrease inherent to the discharge of the discharge capacitance upon firing, and efficient priming of the discharge at higher sustain frequency, also stimulates a fast‐discharge development. Apparently, a “high‐efficiency fast‐discharge mode” exists. It is proposed that in this mode the cathode sheath is not, or incompletely, formed during the increase in the discharge current, and the electric field in the discharge cell is dominated not by the space charges but by the externally applied voltage. The effective discharge field is lowered, resulting in a lower effective electron temperature and more efficient Xe excitation. Also, under a fast discharge build‐up condition, the electron‐heating efficiency increases, due to a decrease in the ion heating losses in the cathode sheath. In a 4‐in. color plasma‐display test panel, operating in a high‐efficiency discharge mode and containing a 50%Xe in Ne gas mixture, a panel efficacy of 5 lm/W concurrent with a luminance of 5000 cd/m² was realized. This result was obtained at a sustain voltage of 260 V. These data compare favorably with alternative high‐efficacy panel design approaches.     

Biased scan of plasma display panel for data voltage reduction

This paper proposes a method of reducing the data voltage V_d of plasma display panels (PDPs). The proposed biased-scan method uses two separate ground systems: one for the sustain pulse generator (FGND) and the other for the data address and control systems (CHGND). A dc voltage bias, which is applied between CHGND and FGND during the address period, reduces V_d while preventing the undesired glow discharge induced by a scan pulse only. CHGND is connected to FGND for the first sustain pulse of each subfield, which reduces the time lag of address discharge, but it is separated from FGND for the other sustain pulses to increase the margin of the sustain voltage. The proposed method was tested on a 15% Xe 50-in. Full HD (1920 × 1080) single-scan PDP which had a sustain discharge gap of 110 μm. V_d could be reduced by 20 V (30%), and the power consumption of the V_d voltage source decreased by ∼25 W (50%) from that of the conventional method.     

A self‐reset ambient‐light sensor system for low‐temperature polycrystalline‐silicon active‐matrix displays

Abstract— A new digital ambient‐light sensor system has been designed and fabricated on a glass substrate using a conventional low‐temperature polycrystalline‐silicon (LTPS) technology. In the proposed system, analog‐to‐digital conversion (ADC) is performed in the time domain instead of the voltage domain and is combined with a light‐detection process. The proposed system employs self‐reset architecture and requires only one comparator for n‐bit digital output. Because the complex analog circuitry is eliminated from the system, it can be readily integrated on the glass substrate.