SOI MOSFET器件的热载流子退化机理

介绍了绝缭体上硅（SOI）材料的制作方法．阐进了SOIMOSFET器件的热载流子注入效应的失效机理。研究表明：前沟和背面缺陷的耦合效应是SOI器件的特有现象．对SOI器件的退化构成潜在的威胁。虽然失效机理比体硅器件复杂,但并不会阻碍高性能、低电压ULSI SOI电路的发展。     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

A thorough investigation of the degradation induced by hot-carrierinjection in deep submicron N- and P-channel partially and fullydepleted unibond and SIMOX MOSFETs

A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V _d=V_t,V_d/2 or V_d) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO₂ interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress     

Successive charging/discharging of gate oxides in SOI MOSFET's bysequential hot-electron stressing of front/back channel

Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes     

Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs

A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.     

Analytical expressions for subthreshold charges and currents in thin-film SOI MOSFETs

Analytical expressions for the front and back channel charges and currents in thin-film SOI MOSFETs operating in the subthreshold region are presented, based on a charge sheet model. The analysis includes the charge coupling between the front and back gates and the effect of interface states.<>     

On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

Buried-oxide charge trapping induced performance degradation infully-depleted ultra-thin SOI p-MOSFET's

The buried-oxide charge trapping induced performance degradation was studied in fully-depleted, ultra-thin SOI p-MOSFET's fabricated on SIMOX wafers. The trapped holes were introduced by X-ray irradiation, and the trapped electrons were introduced by hot hole impact ionization. Subthreshold slope and current drive degradations were observed due to hole-trapping in the buried oxide, via electrostatic coupling between the front and back interfaces. Simulation results showed much reduced performance degradation in SOI p-MOSFET's using thin buried oxides. A minimal interaction of front-channel hot-carrier and radiation effects on the buried oxide degradation, was observed in 0.3-μm channel length transistors     

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.     

A¨nalysis of floating body effects in thin film conventionaland single pocket SOI MOSFETs using the GIDL current technique

Using a novel gate-induced-drain-leakage (GIDL) current technique and two-dimensional (2-D) simulations, single pocket (SP) SOI MOSFETs have been shown to exhibit reduced floating body effects compared to the homogeneously-doped channel (conventional) SOI MOSFETs. The GIDL current technique has been used to characterize the parasitic bipolar transistor gain for both conventional and SP-SOI MOSFETs. From 2-D device simulations, the lower floating body effects in SP-SOI MOSFETs are analyzed and compared with the conventional MOSFETs     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

Dose rate dependence of the back gate degradation in thin gate oxide PD-SOI MOSFETs by 2-MeV electron irradiation

The degradation of the electrical properties of thin gate oxide PD-SOI n-MOSFETs by 2-MeV electrons at different dose rates is presented. The degradation of the back channel and its dependence on dose rate are clarified. The characteristics of the PD-SOI MOSFETs are degraded, and the degradation becomes higher for a low dose rate. The magnitude of the hysteresis characteristics in the drain current becomes smaller after irradiation, and the degradation for a low dose rate is higher than for a high dose rate. It is found that the degradation of the front characteristics is related to the back gate degradation by the coupling effect.     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces

The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface.     

New numerical low frequency noise model for front and buried oxide trap density characterization in FDSOI MOSFETs

In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.     

A method for the prediction of hot-carrier lifetime in floating SOINMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs