Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low-K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low-K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low-K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low-K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low-K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.     

Evaluation of reliability and metallurgical integrity of wire bonds and lead free solder joints on flexible printed circuit board sample modules

This paper presents a study of the optimization of the gold plating thickness for the use of both wire bonding and soldered interconnects on a flexible printed circuit board sample module. Wire bondability is typically better, when the gold plating thickness is greater than 30 μin.; however, the risk of problems with solder joint embrittlement becomes a concern with thick gold plating. In order to better understand the effect of the gold plating thickness on wire bondability and solder joint embrittlement, an evaluation was performed on samples with three ranges of gold plating thicknesses (10–20 μin., 20–30 μin., and 30–45 μin.), on flexible printed circuit board (PCB), substrates. Mechanical shear testing and metallurgical analyses were conducted on chip component solder joints in this three thickness gold study. Thermal shock and drop testing were conducted to evaluate the reliability of the sample modules. Drop testing is especially critical for determining the reliability of the sample modules, which are used in portable consumer electronics products. Reliability testing and metallurgical analyses have been performed to characterize the effect of gold embrittlement on the mechanical integrity of the solder joints with a gold content ranging from 1 to 4 wt.%.     

Oxidation of copper pads and its influence on the quality of Au/Cu bonds during thermosonic wire bonding process

To understand the copper oxide effect on the bondability of gold wire onto a copper pad, thermosonic gold wire bonding to a copper pad was conducted at 90–200 °C under an air atmosphere. The bondability and bonding strength of the Au/Cu bonds were investigated. The bondability and bonding strength were far below the minimum requirements stated in industrial codes. At elevated bonding temperature of 200 °C, the bondability and bonding strength deteriorated mainly due to hydroxide and copper oxide formation on the copper pad. Oxide formation occurred if no appropriate oxide preventive schemes were applied. At lower bonding temperature, 90 °C, poor bondability and low bonding strength were mainly attributed to insufficient thermal energy for atomic inter-diffusion between the gold ball and copper pad.Copper pad oxidation was investigated using an electron spectroscopy for chemical analysis (ESCA) and thermogravimetric analysis (TGA). An activation energy of 35 kJ/mol for copper pad oxidation was obtained from TGA. This implies that different mechanisms govern the oxidation of copper pad and bulk copper. Hydroxide and copper oxide were identified based on the shifted binding energy. Cu(OH)₂ forms mainly on the top surface of copper pads and the underlying layer consists mainly of CuO. The hydroxide concentration increased with increasing the heating temperatures. After heating at 200 °C, the hydroxide concentration on the copper pad surface was approximately six times that at 90 °C. Protective measures such as passivation layer deposition or using shielding gas are critical for thermosonic wire bonding on chips with copper interconnects.     

Effects of Cu/Al intermetallic compound (IMC) on copper wire and aluminum pad bondability

Copper wire bonding is an alternative interconnection technology that serves as a viable, and cost saving alternative to gold wire bonding. Its excellent mechanical and electrical characteristics attract the high-speed, power management devices and fine-pitch applications. Copper wire bonding can be a potentially alternative interconnection technology along with flip chip interconnection. However, the growth of Cu/Al intermetallic compound (IMC) at the copper wire and aluminum interface can induce a mechanical failure and increase a potential contact resistance. In this study, the copper wire bonded chip samples were annealed at the temperature range from 150/spl deg/C to 300/spl deg/C for 2 to 250 h, respectively. The formation of Cu/Al IMC was observed and the activation energy of Cu/Al IMC growth was obtained from an Arrhenius plot (ln (growth rate) versus 1/T). The obtained activation energy was 26Kcal/mol and the behavior of IMC growth was very sensitive to the annealing temperature. To investigate the effects of IMC formation on the copper wire bondability on Al pad, ball shear tests were performed on annealed samples. For as-bonded samples, ball shear strength ranged from 240-260gf, and ball shear strength changed as a function of annealing times. For annealed samples, fracture mode changed from adhesive failure at Cu/Al interface to IMC layer or Cu wire itself. The IMC growth and the diffusion rate of aluminum and copper were closely related to failure mode changes. Micro-XRD was performed on fractured pads and balls to identify the phases of IMC and their effects on the ball bonding strength. From XRD results, it was confirmed that the major IMC was /spl gamma/-Cu/sub 9/Al/sub 4/ and it provided a strong bondability.     

Process windows for low-temperature Au wire bonding

The process windows are presented for low-temperature Au wire bonding on Au/Ni/Cu bond pads of varying Au-layer thicknesses metallized on an organic FR-4 printed circuit board (PCB). Three different plating techniques were used to deposit the Au layers: electrolytic plating, immersion plating, and immersion plating followed by electrolytic plating. Wide ranges of wire bond force, bond power, and bond-pad temperature were used to identify the combination of these processing parameters that can produce good wire bonds, allowing the construction of process windows. The criterion for successful bonds is no peel off for all 20 wires tested. The wire pull strengths and wire deformation ratios are measured to evaluate the bond quality after a successful wire bond. Elemental and surface characterization techniques were used to evaluate the bond-pad surfaces and are correlated to wire bondability and wire pull strength. Based on the process windows along with the pull strength data, the bond-pad metallization and bonding conditions can be further optimized for improved wire bondability and product yields. The wire bondability of the electrolytic bond pad increased with Au-layer thickness. The bond pad with an Au-layer thickness of 0.7 μm displayed the highest bondability for all bonding conditions used. The bondability of immersion bond pads was comparable to electrolytic bond pads with a similar Au thickness. Although a high temperature was beneficial to wire bondability with a wide process window, it did not improve the bond quality as measured by wire pull strength.     

Modular sensor chip design for package stress evaluation and reliability characterisation

A modular test chip comprising an array of 2 mm square modules has been designed and fabricated. The maximum chip size can be up to 10 mm square, i.e. a 5 × 5 array of modules. The motivation behind the test chip is primarily the need to address reliability concerns in the use of copper wire bonding. It is known that the move to replace gold wire bonding with copper, driven primarily by the escalating price of gold, leads to reliability challenges at the interfaces between the wire bonds, the bond pads and the mould compound. Its function is to address. The chip comprises daisy chain structures to monitor changes of wire bond resistance and leakage current, large and small area stress sensors to measure stress on the chip associated with die attach and moulding, and comb and triple track sensors to study corrosion and moisture penetration related to mould compound.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-/spl mu/m 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembly with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.     

Investigation of Thermosonic Wire Bonding Resistance of Gold Wire Onto Copper Pad

This paper discusses the electric performance for thermosonic wire bonding of gold wire onto copper pads. Various methods normally used to improve bondability were investigated including the bare copper pads with argon shielding gas and the copper pads with cupric oxide film, cuprous oxide film, and silver film. The micro-contact theory was used to determine the effective contact area. The circuit contact resistance was measured for each sample and was presented in terms of ultrasound power and effective contact area. The results show that the increase in the effective contact area leads to a lower circuit contact resistance before reaching a minimum value, and further increase in the effective contact area would not have noticeable effect on the resistance.      

High-performance FCBGA based on multi-layer thin-substrate packaging technology

We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T_g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning.We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.     

A power-constrained design strategy for CMOS tuned low noise amplifiers

This paper presents a design methodology for tuned low noise amplifiers (LNAs), based on the minimization of the noise figure for a given power consumption. Our proposed design strategy is demonstrated through the design of a 2.4 GHz LNA. Simulation results show that the amplifier draws 5 mA from a 3.3 V supply voltage and features a 1.7 dB noise figure, while keeping the input/output impedance matched to 50 Ω. The circuit achieves a gain of 11dB and a 1dB compression point of about −5 dB m. Custom ESD structures that do not degrade excessively the LNA performance are used for protection. The chip area (excluding the bonding pads) is approximately 0.3 × 0.3 mm².     

Increasing bondability and bonding strength of gold stud bumps onto copper pads with a deposited titanium barrier layer

A flip-chip assembly is an attractive scheme for use in high performance and miniaturized microelectronics packaging. Wafer bumping is essential before chips can be flip-bonded to a substrate. Wafer bumping can be used for mechanical-single point stud bump bonding (SBB), and is based on conventional thermosonic wire bonding. This work proposes depositing a titanium barrier layer between the copper film and the silver bonding layer to achieve perfect bondability and sufficiently strong thermosonic bonding between a stud bump and the copper pad.A titanium layer was deposited on the copper pads to prevent copper atoms from out-diffusing during thermosonic stud bump bonding. A silver film was then deposited on the surface of the titanium film as a bonding layer to increase the bondability and bonding strength for stud bumps onto copper pads. The integration of the silver bonding layer with a diffusion barrier layer of titanium on the copper pads yielded 100% bondability between the stud bump and pads. The strength of bonding between the gold bumps on the copper pads significantly exceeds the minimum average values in JEDEC specifications. The diffusion barrier layer of titanium effectively prevents copper atoms from out-diffusing to the silver bonding layer surface during thermosonic bonding, which fact can be interpreted with reference to the experimental results of energy dispersive spectrometry (EDS) and analyses of Auger depth profiles. This diffusion barrier layer of titanium efficiently provides perfect bondability and sufficiently strong bonding between a stud bump and copper pads with a silver bonding layer.     

Effect of plasma treatment of Au-Ni-Cu bond pads on process windows of Au wire bonding

The wire bondability of Au-Ni-Cu bond pads with different Au plating schemes, including electrolytic and immersion plates, are evaluated after plasma treatment. The plasma cleaning conditions, such as cleaning power and time, are optimized based on the process window and wire pull strength measurements for different bond pad temperatures. Difference in the efficiency of plasma treatment in improving the wire bondability for different Au plates is identified. The plasma-cleaned bond pads are exposed to air to evaluate the recontamination process and the corresponding degradation of wire pull strength. The changes in bond pad surface characteristics, such as surface free energy and polar functionality, with exposure time are correlated to the wire pull strength, which in turn provides practical information about the shelf life of wire bonding after plasma cleaning.     

The effect of prebonding heat treatment on the separability of Auwire from Ag-plated Cu alloy substrate

The wire bonding technology that relies on subsequent wire separation of a connection has a possibility of becoming a key packaging technology in the environmentally friendly aspects of the recycling of mounting materials, such as the reworking of chip on board (COB) mounting and the application of the inter-poserless chip size package (CSP) in the manufacturing process. This study investigated how heat treatment before bonding affects separability at the ball bonding area. For the investigation, we used bonding pairs of Ag-plated Cu alloy substrate and An wire. Heating a board to 150°C before wire bonding degraded wire bondability but improved separability. An analysis of Ag plating by Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS) revealed that the heat treatment caused the Cu on the board to diffuse into the Ag plating and to deposit concentrations of Cu in the form of Cu(OH)₂ and CuCl₂ on the Ag surface     

Thermosonic bonding of gold wire onto a copper pad with titanium thin-film deposition

A novel thermosonic (TS) bonding process for gold wire bonded onto chips with copper interconnects was successfully developed by depositing a thin, titanium passivation layer on a copper pad. The copper pad oxidizes easily at elevated temperature during TS wire bonding. The bondability and bonding strength of the Au ball onto copper pads are significantly deteriorated if a copper-oxide film exists. To overcome this intrinsic drawback of the copper pad, a titanium thin film was deposited onto the copper pad to improve the bondability and bonding strength. The thickness of the titanium passivation layer is crucial to bondability and bonding strength. An appropriate, titanium film thickness of 3.7 nm is proposed in this work. One hundred percent bondability and high bonding strength was achieved. A thicker titanium film results in poor bond-ability and lower bonding strength, because the thicker titanium film cannot be removed by an appropriate range of ultrasonic power during TS bonding. The protective mechanism of the titanium passivation layer was interpreted by the results of field-emission Auger electron spectroscopy (FEAES) and electron spectroscopy for chemical analysis (ESCA). Titanium dioxide (TiO₂), formed during the die-saw and die-mount processes, plays an important role in preventing the copper pad from oxidizing. Reliability of the high-temperature storage (HTS) test for a gold ball bonded on the copper pad with a 3.7-nm titanium passivation layer was verified. The bonding strength did not degrade after prolonged storage at elevated temperature. This novel process could be applied to chips with copper interconnect packaging in the TS wire-bonding process.     

Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

Direct gold and copper wires bonding on copper

The key to bonding to copper die is to ensure bond pad cleanliness and minimum oxidation during wire bonding process. This has been achieved by applying a organic coating layer to protect the copper bond pad from oxidation. During the wire bonding process, the organic coating layer is removed and a metal to metal weld is formed. This organic layer is a self-assembled monolayer. Both gold and copper wires have been wire-bonded successfully to the copper die even without prior plasma cleaning. The ball diameter for both wires are 60 μm on a 100 μm fine pitch bond pad. The effectiveness of the protection of the organic coating layer starts from the wafer dicing process up to the wire bonding process and is able to protect the bond pad for an extended period after the first round of wire bond process. In this study, oxidization of copper bond pad at different packaging processing stages, dicing and die attach curing, have been explored. The ball shear strength for both gold and copper ball bonds achieved are 5 and 6 g/mil² respectively. When subjected to high temperature storage test at 150 °C, the ball bonds formed by both gold and copper wire bond on the organic coated copper bondpad are thermally stable in ball shear strength up to a period of 1440 h. The encapsulated daisy chain test vehicle with both gold and copper wires bonding have passed 1000 cycles of thermal cycling test (−65 to 150 °C). It has been demonstrated that orientation imaging microscopy technique is able to detect early levels of oxidation on the copper bond pad. This is extremely important in characterization of the bondability of the copper bond pad surface.     

Effects of metallization characteristics on gold wire bondability of organic printed circuit boards

Organic printed circuit boards (PCBs) with Au/Ni plates on bond pads are widely used in chip-on-board (COB), ball grid array (BGA), and chip-scale packages. These packages are interconnected using thermosonic gold wire bonding. The wire bond yield relies on the bondability of the Ni/Au pads. Several metallization parameters, including elemental composition, thickness, hardness, roughness, and surface contamination, affect the success of the solid state joining process. In this study, various characterization and mechanical testing techniques are employed to evaluate these parameters for different metallization schemes with varying Ni and Au layer thicknesses. The pull force of Au wires is measured as a function of plasma treatment applied before wire bonding to clean the bond pads. Close correlations are established between metallization characteristics and wire bond quality.     

The development of Cu bonding wire with oxidation-resistant metal coating

Although Cu bonding wire excels over Au bonding wire in some respects such as production costs, it has not been widely used because of its poor bondability at second bonds due to surface oxidation. We conceived an idea of electroplating oxidation-resistant metal on the Cu bonding wire to prevent the surface oxidation. The electroplating of Au, Ag, Pd, and Ni over Cu bonding wire all increased bond strengths as expected, but it caused problematic ball shapes except Pd-plated Cu bonding wire. The wire could produce the same ball shape as that of Au bonding wire. It was also proved to have excellent bondability sufficient to replace Au bonding wire. That is, it excelled in bond strengths, defective bonding ratio, and wideness of "Parameter Windows". It also showed the same stability as Au bonding wire in reliability tests, while bonds of Cu bonding wire were deteriorated in a few of the tests. In short, the Pd-plated Cu bonding wire can realize excellent bonding similar to Au bonding wire, while having much lower production costs.     

Single-shot, high repetition rate metallic pattern transfer

A flexible high-speed fabrication of relatively thick (about 1 μm) and large (about 120×120 μm) thin film metal pads with a laser-induced forward transfer technique using femtosecond laser pulses (fs-LIFT) will be discussed. Possible applications are thickening of thin film contact pads for wire bonding, the deposition of solder pads or the frequency or electrical resistance tuning of discrete devices. The use of ultrashort laser pulses instead of nanosecond laser pulses reduces the melting problem, increases the quality and the adhesion of the transferred metal pads and allows the transfer of complete disks out of thin films (<1 μm thickness). The combination of ultrashort laser pulses with a pre-structuring of the metal film improves the geometry of the pads and increases the film disk thickness (>1 μm). As a example the transfer of 0.76- and 1.8 μm thick gold/tin disks with a single laser pulse are presented.